Attention is currently required from: Nick Vaccaro, Kyösti Mälkki. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59011 )
Change subject: mb/google,intel: Split chromeos.c files ......................................................................
Patch Set 6:
(3 comments)
File src/mainboard/google/dedede/chromeos.c:
https://review.coreboot.org/c/coreboot/+/59011/comment/d87d5354_737e26b7 PS6, Line 15: {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
What is the relevance of passing a GPIO pin number and polarity here? Is the payload able (and platf […]
depthcharge uses this data to re-read the current GPIO state if applicable (there is a `resample_at_runtime` flag in depthcharge).
lb_gpio may only be used with depthcharge, but I wouldn't say that makes it obsolete 😊
File src/mainboard/google/eve/chromeos.c:
https://review.coreboot.org/c/coreboot/+/59011/comment/b2d0c4d4_b4887728 PS6, Line 26: CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
I understand this fills CRHW.GPIO sysfs subtree with chromeos_acpi driver. […]
Yes, the `crossystem` userspace utility reads the ACPI package and then it can read the GPIOs again if desired:
https://chromium.googlesource.com/chromiumos/platform/vboot_reference/+/refs...
File src/mainboard/google/parrot/chromeos.c:
https://review.coreboot.org/c/coreboot/+/59011/comment/9e5ce95c_99fecfcf PS6, Line 25: {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"},
GPIO pin 101? Should these non-GPIO pins be -1 for virtual?
maybe the PB was wired up to the PCH as well? not sure, but it does look fishy
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Tim Wawrzynczak (Code Review)