Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35641 )
Change subject: nb/intel/x4x: Avoid x4x.h header with romcc-bootblock ......................................................................
nb/intel/x4x: Avoid x4x.h header with romcc-bootblock
Change-Id: If8b70298bffd72d1de7f74917131d648c5fcab66 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/northbridge/intel/x4x/bootblock.c 1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35641/1
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 1dfdf19..e733287 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -16,7 +16,10 @@
#include <device/pci_ops.h> #include "iomap.h" -#include "x4x.h" + +/* Just re-define these instead of including x4x.h. It blows up romcc. */ +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64
static void bootblock_northbridge_init(void) {
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35641 )
Change subject: nb/intel/x4x: Avoid x4x.h header with romcc-bootblock ......................................................................
Patch Set 1: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35641 )
Change subject: nb/intel/x4x: Avoid x4x.h header with romcc-bootblock ......................................................................
nb/intel/x4x: Avoid x4x.h header with romcc-bootblock
Change-Id: If8b70298bffd72d1de7f74917131d648c5fcab66 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35641 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/x4x/bootblock.c 1 file changed, 4 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 1dfdf19..e733287 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -16,7 +16,10 @@
#include <device/pci_ops.h> #include "iomap.h" -#include "x4x.h" + +/* Just re-define these instead of including x4x.h. It blows up romcc. */ +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64
static void bootblock_northbridge_init(void) {
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)