Change in coreboot[master]: soc/amd/common/espi: Reset eSPI registers to known state

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52058 )

Change subject: soc/amd/common/espi: Reset eSPI registers to known state
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Patch Set 4:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/52058/comment/ab685a53_833d199d 
PS2, Line 9: This sets the eSPI registers to the reset values specified in the PPR.
           : 
           : On Cezanne, the PSP modifies these registers such that the eSPI
> Why is the PSP writing to port80?

The PSP writes port 80s to signal where it in the boot processes. i.e., sign of life, memory training, etc. It uses 16 MHz and single IO mode. We don't currently get these eport 80s on the ChromeEC. See b/181598456.