Attention is currently required from: Ravi Kumar Bokka, Hung-Te Lin, Paul Menzel, Rex-BC Chen, Julius Werner, Arthur Heymans, Yu-Ping Wu, Jianjun Wang.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )
Change subject: coreboot_tables: Add PCIe info to coreboot table
......................................................................
Patch Set 20:
(1 comment)
Patchset:
PS20:
Starting a new comment thread, to not further interleave the discussions.
struct lb_mtk_pcie {
uint32_t tag;
uint32_t size;
lb_uint64_t pcie_ctrl_base;
uint32_t config_offset;
uint32_t cfgnum_offset; // maybe this can change each gen too?
};
That way, the information to change the BDF config space points to and the offset to config space are known, is that sufficient for MTK?
That's sufficient for our current PCIe IP, but since we will not change the config_offset and cfgnum_offset on this PCIe IP, I'm not sure if we really need to pass these two offsets through the structure.
We can also start with `pcie_ctrl_base` and extend the struct later if
ever needed. The ABI would stay backwards compatible. Only consumers
should check for a minimum size, not a specific one (e.g. `size >= 16`
instead of `size == 16`).
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