Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37292 )
Change subject: scpu/amd/{agesa,pi}/Kconfig: select SSE2 ......................................................................
scpu/amd/{agesa,pi}/Kconfig: select SSE2
SSE2 instructions are supported by family14 and newer.
SSE will be automatically enabled in bootblock_crt0 for platforms that migrate to C bootblock. Because of that family specific CAR setup may avoid additional code.
TEST=boot PC Engines apu1 and apu2
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I19f1793112439f0c706ebb066f9807364ad8c5a7 --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37292/1
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index ddfe707..9956579 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -29,6 +29,7 @@ select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select SSE2
if CPU_AMD_AGESA
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index d18f873..728c7b1 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -28,6 +28,7 @@ select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select SSE2
if CPU_AMD_PI
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37292 )
Change subject: scpu/amd/{agesa,pi}/Kconfig: select SSE2 ......................................................................
Patch Set 1: Code-Review+1
Hello Kyösti Mälkki, Arthur Heymans, Marshall Dawson, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37292
to look at the new patch set (#2).
Change subject: cpu/amd/{agesa,pi}/Kconfig: select SSE2 ......................................................................
cpu/amd/{agesa,pi}/Kconfig: select SSE2
SSE2 instructions are supported by family14 and newer.
SSE will be automatically enabled in bootblock_crt0 for platforms that migrate to C bootblock. Because of that family specific CAR setup may avoid additional code.
TEST=boot PC Engines apu1 and apu2
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I19f1793112439f0c706ebb066f9807364ad8c5a7 --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37292/2
Hello Kyösti Mälkki, Arthur Heymans, Marshall Dawson, build bot (Jenkins), Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37292
to look at the new patch set (#3).
Change subject: cpu/amd/{agesa,pi}/Kconfig: select SSE2 ......................................................................
cpu/amd/{agesa,pi}/Kconfig: select SSE2
SSE2 instructions are supported by family14 and newer.
SSE will be automatically enabled in bootblock_crt0 for platforms that migrate to C bootblock. Because of that family specific CAR setup may avoid additional code.
TEST=boot PC Engines apu1 and apu2
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I19f1793112439f0c706ebb066f9807364ad8c5a7 --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37292/3
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37292 )
Change subject: cpu/amd/{agesa,pi}/Kconfig: select SSE2 ......................................................................
Patch Set 3:
Did you check if romcc bootblocks remain unchanged?
ifeq ($(CONFIG_SSE),y) bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__BOOTBLOCK__ endif
Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37292 )
Change subject: cpu/amd/{agesa,pi}/Kconfig: select SSE2 ......................................................................
Patch Set 3:
Patch Set 3:
Did you check if romcc bootblocks remain unchanged?
ifeq ($(CONFIG_SSE),y) bootblock_romccflags := -mcpu=k7 -mno-mmx -msse -O2 -D__BOOTBLOCK__ endif
Booted PC Engines apu1 with romcc bootblock. Works well.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37292 )
Change subject: cpu/amd/{agesa,pi}/Kconfig: select SSE2 ......................................................................
Patch Set 4: Code-Review+2
Kyösti Mälkki has uploaded a new patch set (#5) to the change originally created by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/37292 )
Change subject: cpu/amd/{agesa,pi}/Kconfig: select SSE2 ......................................................................
cpu/amd/{agesa,pi}/Kconfig: select SSE2
SSE2 instructions are supported by family14 and newer.
SSE will be automatically enabled in bootblock_crt0 for platforms that migrate to C bootblock. Because of that family specific CAR setup may avoid additional code.
TEST=boot PC Engines apu1 and apu2
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I19f1793112439f0c706ebb066f9807364ad8c5a7 --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37292/5
Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37292 )
Change subject: cpu/amd/{agesa,pi}/Kconfig: select SSE2 ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37292 )
Change subject: cpu/amd/{agesa,pi}/Kconfig: select SSE2 ......................................................................
cpu/amd/{agesa,pi}/Kconfig: select SSE2
SSE2 instructions are supported by family14 and newer.
SSE will be automatically enabled in bootblock_crt0 for platforms that migrate to C bootblock. Because of that family specific CAR setup may avoid additional code.
TEST=boot PC Engines apu1 and apu2
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I19f1793112439f0c706ebb066f9807364ad8c5a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37292 Reviewed-by: Patrick Georgi pgeorgi@google.com Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/pi/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Kyösti Mälkki: Looks good to me, approved
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index ddfe707..9956579 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -29,6 +29,7 @@ select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select SSE2
if CPU_AMD_AGESA
diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index d18f873..728c7b1 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -28,6 +28,7 @@ select SPI_FLASH if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE + select SSE2
if CPU_AMD_PI
-
Arthur Heymans (Code Review) -
Kyösti Mälkki (Code Review)
-
Michał Żygowski (Code Review)
-
Patrick Georgi (Code Review)