HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32423
Change subject: src/northbridge/intel: Remove unused variables ......................................................................
src/northbridge/intel: Remove unused variables
Change-Id: Idd339e324b833d2d024edb45e33c3d74af4473e8 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c 2 files changed, 4 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/32423/1
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index bf00099..48bca36 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -1173,7 +1173,7 @@
static void sdram_rcomp(struct sysinfo *s) { - u8 i, j, reg8, f, rcompp, rcompn, srup, srun; + u8 i, j, reg8, rcompp, rcompn, srup, srun; u16 reg16; u32 reg32, rcomp1, rcomp2;
@@ -1263,10 +1263,8 @@ srun = 0;
if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { - f = 0; rcomp1 = 0x00050431; } else { - f = 1; rcomp1 = 0x00050542; } if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) { @@ -2125,31 +2123,25 @@ reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf0); pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 & ~1);
- u32 nranks, curranksize, maxranksize, maxdra, dra; - u8 rankmismatch, dramismatch; + u32 nranks, curranksize, maxranksize, dra; + u8 rankmismatch; static const u8 drbtab[10] = { 0x4, 0x2, 0x8, 0x4, 0x8, 0x4, 0x10, 0x8, 0x20, 0x10 };
nranks = 0; curranksize = 0; maxranksize = 0; - maxdra = 0; rankmismatch = 0; - dramismatch = 0; FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { nranks++; dra = (u8) ((MCHBAR32(0x208) >> (8*r)) & 0x7f); curranksize = drbtab[dra]; if (maxranksize == 0) { maxranksize = curranksize; - maxdra = dra; } if (curranksize != maxranksize) { rankmismatch = 1; } - if (dra != maxdra) { - dramismatch = 1; - } }
reg8 = 0; @@ -2220,7 +2212,7 @@ static void sdram_new_trd(struct sysinfo *s) { u8 pidelay, i, j, k, cc, trd_perphase[5]; - u8 bypass, freqgb, trd, reg8, txfifo, cas; + u8 bypass, freqgb, trd, reg8, txfifo; u32 reg32, datadelay, tio, rcvendelay, maxrcvendelay; u16 tmclk, thclk, buffertocore, postcalib; static const u8 txfifo_lut[8] = { 0, 7, 6, 5, 2, 1, 4, 3 }; @@ -2236,7 +2228,6 @@
freqgb = 110; buffertocore = 5000; - cas = s->selected_timings.CAS; postcalib = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 1250 : 500; tmclk = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 3000 : 2500; tmclk = tmclk * 100 / freqgb; diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index ce18440..ed372b5 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -282,16 +282,12 @@ u8 dq_lower[TOTAL_BYTELANES]; u8 dq_upper[TOTAL_BYTELANES]; struct dll_setting dq_setting[TOTAL_BYTELANES]; - u8 dq_average; - u32 dq_absolute;
printk(BIOS_DEBUG, "Starting DQ write training\n");
FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { printk(BIOS_DEBUG, "Doing DQ write training on CH%d\n", channel);
- dq_average = 0; - dq_absolute = 0; /* Start all lanes at DQS values */ FOR_EACH_BYTELANE(lane) { dqset(channel, lane, &s->dqs_settings[channel][lane]);
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32423 )
Change subject: src/northbridge/intel: Remove unused variables ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32423 )
Change subject: src/northbridge/intel: Remove unused variables ......................................................................
src/northbridge/intel: Remove unused variables
Change-Id: Idd339e324b833d2d024edb45e33c3d74af4473e8 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/32423 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c 2 files changed, 4 insertions(+), 17 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index bf00099..48bca36 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -1173,7 +1173,7 @@
static void sdram_rcomp(struct sysinfo *s) { - u8 i, j, reg8, f, rcompp, rcompn, srup, srun; + u8 i, j, reg8, rcompp, rcompn, srup, srun; u16 reg16; u32 reg32, rcomp1, rcomp2;
@@ -1263,10 +1263,8 @@ srun = 0;
if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { - f = 0; rcomp1 = 0x00050431; } else { - f = 1; rcomp1 = 0x00050542; } if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) { @@ -2125,31 +2123,25 @@ reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf0); pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 & ~1);
- u32 nranks, curranksize, maxranksize, maxdra, dra; - u8 rankmismatch, dramismatch; + u32 nranks, curranksize, maxranksize, dra; + u8 rankmismatch; static const u8 drbtab[10] = { 0x4, 0x2, 0x8, 0x4, 0x8, 0x4, 0x10, 0x8, 0x20, 0x10 };
nranks = 0; curranksize = 0; maxranksize = 0; - maxdra = 0; rankmismatch = 0; - dramismatch = 0; FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { nranks++; dra = (u8) ((MCHBAR32(0x208) >> (8*r)) & 0x7f); curranksize = drbtab[dra]; if (maxranksize == 0) { maxranksize = curranksize; - maxdra = dra; } if (curranksize != maxranksize) { rankmismatch = 1; } - if (dra != maxdra) { - dramismatch = 1; - } }
reg8 = 0; @@ -2220,7 +2212,7 @@ static void sdram_new_trd(struct sysinfo *s) { u8 pidelay, i, j, k, cc, trd_perphase[5]; - u8 bypass, freqgb, trd, reg8, txfifo, cas; + u8 bypass, freqgb, trd, reg8, txfifo; u32 reg32, datadelay, tio, rcvendelay, maxrcvendelay; u16 tmclk, thclk, buffertocore, postcalib; static const u8 txfifo_lut[8] = { 0, 7, 6, 5, 2, 1, 4, 3 }; @@ -2236,7 +2228,6 @@
freqgb = 110; buffertocore = 5000; - cas = s->selected_timings.CAS; postcalib = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 1250 : 500; tmclk = (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) ? 3000 : 2500; tmclk = tmclk * 100 / freqgb; diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index ce18440..ed372b5 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -282,16 +282,12 @@ u8 dq_lower[TOTAL_BYTELANES]; u8 dq_upper[TOTAL_BYTELANES]; struct dll_setting dq_setting[TOTAL_BYTELANES]; - u8 dq_average; - u32 dq_absolute;
printk(BIOS_DEBUG, "Starting DQ write training\n");
FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { printk(BIOS_DEBUG, "Doing DQ write training on CH%d\n", channel);
- dq_average = 0; - dq_absolute = 0; /* Start all lanes at DQS values */ FOR_EACH_BYTELANE(lane) { dqset(channel, lane, &s->dqs_settings[channel][lane]);
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)