[XS] Change in coreboot[main]: mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin

[Li1 Feng (Code Review)]

Attention is currently required from: Bora Guvendik, Jayvik Desai, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Subrata Banik.

Li1 Feng has posted comments on this change by Li1 Feng. ( https://review.coreboot.org/c/coreboot/+/86005?usp=email )

Change subject: mb/google/fatcat/var/fatcat: disable ISH UART0 RX pin
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Patch Set 5:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86005/comment/24a01272_f027f20c?usp... :
PS2, Line 7: fatcat-ish
> Please use a longer prefix. `git log --oneline` should show you kind of a template.

Done

https://review.coreboot.org/c/coreboot/+/86005/comment/4c5d200e_bc3a0174?usp... :
PS2, Line 11: causing ISH low power mode failure
> How is this failure detected?

ISH console log shows it hang during boot up; not able to register with cros_ec.

File src/mainboard/google/fatcat/variants/fatcat/fw_config.c:

https://review.coreboot.org/c/coreboot/+/86005/comment/ab287523_b0bfecee?usp... :
PS2, Line 432: 	/* GPP_D05:     ISH_UART0_RXD */
             : 	PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2),
> > We still have ISH log, just console doesn't accept input. […]

Added this to comment. In any case, like for debug purpose, if we want to input to console working, we can revert this change(better be local change) and make sure ISH DIP switch setting is ON.