Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29680
Change subject: Kconfig: Unify power-after-failure options ......................................................................
Kconfig: Unify power-after-failure options
The newest and most useful incarnation was hiding in soc/intel/common/. We move it into the Mainboard menu and extend it with various flags to be selected to control the default and which options are visible. Also add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the boolean to int conversion into Kconfig: 0 - S5 1 - S1 2 - previous state
This patch focuses on the Kconfig code. The C code could be unified as well, e.g. starting with a common enum and safe wrapper around the get_option() call.
TEST=Did what-jenkins-does with and without this commit and compared binaries. Nothing changed for the default configurations.
Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/Kconfig M src/mainboard/asus/kcma-d8/Kconfig M src/mainboard/asus/kfsn4-dre/Kconfig M src/mainboard/asus/kgpe-d16/Kconfig M src/mainboard/msi/ms9652_fam10/Kconfig M src/mainboard/samsung/lumpy/Kconfig M src/mainboard/samsung/stumpy/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smihandler.c M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmclib.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/amd8111/Kconfig M src/southbridge/amd/amd8111/acpi.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/sb700/Kconfig M src/southbridge/amd/sb700/sm.c M src/southbridge/amd/sb800/sm.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/pmutil.h M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/fsp_bd82x6x/Kconfig M src/southbridge/intel/fsp_bd82x6x/lpc.c M src/southbridge/intel/fsp_bd82x6x/pch.h M src/southbridge/intel/fsp_bd82x6x/smihandler.c M src/southbridge/intel/fsp_i89xx/Kconfig M src/southbridge/intel/fsp_i89xx/lpc.c M src/southbridge/intel/fsp_i89xx/pch.h M src/southbridge/intel/fsp_i89xx/smihandler.c M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/i82801dx/Kconfig M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801dx/smihandler.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801gx/smihandler.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/Kconfig M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/nvidia/ck804/Kconfig M src/southbridge/nvidia/ck804/lpc.c M src/southbridge/nvidia/mcp55/Kconfig M src/southbridge/nvidia/mcp55/lpc.c M src/superio/nuvoton/nct5572d/Kconfig M src/superio/nuvoton/nct5572d/superio.c M src/superio/winbond/w83667hg-a/Kconfig M src/superio/winbond/w83667hg-a/superio.c 62 files changed, 145 insertions(+), 171 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29680/1
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index 04dca4a..cd488f2 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -180,3 +180,59 @@ config ENABLE_POWER_BUTTON def_bool y if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_ENABLE def_bool n if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_DISABLE + +config HAVE_POWER_STATE_AFTER_FAILURE + bool + +if HAVE_POWER_STATE_AFTER_FAILURE + +config HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + bool + +config POWER_STATE_DEFAULT_ON_AFTER_FAILURE + bool + help + Selected by mainboards that want to override a "default off" + that was set at chip level. + +config POWER_STATE_DEFAULT_OFF_AFTER_FAILURE + bool + help + Selected by mainboards or chips that want a "default off" behaviour. + +choice + prompt "System Power State after Failure" + default POWER_STATE_OFF_AFTER_FAILURE \ + if !POWER_STATE_DEFAULT_ON_AFTER_FAILURE && \ + POWER_STATE_DEFAULT_OFF_AFTER_FAILURE + default POWER_STATE_ON_AFTER_FAILURE + +config POWER_STATE_OFF_AFTER_FAILURE + bool "S5 Soft Off" + help + Choose this option if you want to put system into + S5 after reapplying power after failure. + +config POWER_STATE_ON_AFTER_FAILURE + bool "S0 Full On" + help + Choose this option if you want to keep system in + S0 after reapplying power after failure. + +config POWER_STATE_PREVIOUS_AFTER_FAILURE + bool "Keep Previous State" + depends on HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + help + Choose this option if you want to keep system in the + same power state as before failure after reapplying + power. + +endchoice + +config MAINBOARD_POWER_FAILURE_STATE + int + default 2 if POWER_STATE_PREVIOUS_AFTER_FAILURE + default 1 if POWER_STATE_ON_AFTER_FAILURE + default 0 + +endif # HAVE_POWER_STATE_AFTER_FAILURE diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig index f20cf21..712755e 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -32,6 +32,7 @@ select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT + select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
config MAINBOARD_DIR string @@ -90,10 +91,6 @@ bool default y
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default y - config MAX_REBOOT_CNT int default 10 diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index 55bd5c3..1597d1c 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -19,6 +19,7 @@ select ENABLE_APIC_EXT_ID select DRIVERS_I2C_W83793 select DRIVERS_XGI_Z9S + select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
config MAINBOARD_DIR string @@ -80,10 +81,6 @@ bool default y
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default y - config MAX_REBOOT_CNT int default 10 diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 8028849..b21f8ad 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -33,6 +33,7 @@ select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT + select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
config MAINBOARD_DIR string @@ -95,10 +96,6 @@ string default "1a03,2000"
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default y - config MAX_REBOOT_CNT int default 10 diff --git a/src/mainboard/msi/ms9652_fam10/Kconfig b/src/mainboard/msi/ms9652_fam10/Kconfig index 080fc58..6cf8606 100644 --- a/src/mainboard/msi/ms9652_fam10/Kconfig +++ b/src/mainboard/msi/ms9652_fam10/Kconfig @@ -20,6 +20,7 @@ select LIFT_BSP_APIC_ID select IOAPIC select SMP + select POWER_STATE_DEFAULT_ON_AFTER_FAILURE
config MAINBOARD_DIR string @@ -59,10 +60,6 @@ int default 9
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default y - config USBDEBUG bool default n diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 9cb0e5f..6829ecc 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -44,10 +44,6 @@ string default "pci8086,0106.rom"
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default n - if EARLY_PCI_BRIDGE
config EARLY_PCI_BRIDGE_DEVICE diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index f0ac4f7..49210bc 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -42,8 +42,4 @@ string default "pci8086,0106.rom"
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL - bool - default n - endif # BOARD_SAMSUNG_STUMPY diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 18ec51f..3f06d4a 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -40,6 +40,9 @@ select HAVE_SPI_CONSOLE_SUPPORT select CPU_INTEL_COMMON select INTEL_GMA_ACPI + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
config PCIEXP_ASPM bool diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 87aaf6b..762198b1 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -152,7 +152,7 @@ const char *state; /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
/* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c index 24f6a3d..1ba2bdd 100644 --- a/src/soc/intel/broadwell/smihandler.c +++ b/src/soc/intel/broadwell/smihandler.c @@ -156,7 +156,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
/* save and recover RTC port values */ u8 tmp70, tmp72; diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 9b21010..4569525 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -213,6 +213,7 @@ * 0 == S5 Soft Off * 1 == S0 Full On * 2 == Keep Previous State + * Keep in sync with `config MAINBOARD_POWER_FAILURE_STATE`. */ enum { MAINBOARD_POWER_STATE_OFF, diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index 2f08408..244f59c 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -2,35 +2,12 @@ depends on SOC_INTEL_COMMON_BLOCK_GPIO depends on ACPI_INTEL_HARDWARE_SLEEP_VALUES bool + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE help Intel Processor common code for Power Management controller(PMC) subsystem
-choice - prompt "System Power State after Failure" - default POWER_STATE_ON_AFTER_FAILURE - -config POWER_STATE_OFF_AFTER_FAILURE - bool "S5 Soft Off" - help - Choose this option if you want to keep system into - S5 after reapplying power after failure - -config POWER_STATE_ON_AFTER_FAILURE - bool "S0 Full On" - help - Choose this option if you want to keep system into - S0 after reapplying power after failure - -config POWER_STATE_PREVIOUS_AFTER_FAILURE - bool "Keep Previous State" - help - Choose this option if you want to keep system into - same power state as before failure even after reapplying - power - -endchoice - config PMC_INVALID_READ_AFTER_WRITE bool default n diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index ef4384d..dcc7cc9 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -587,10 +587,5 @@ */ int pmc_get_mainboard_power_failure_state_choice(void) { - if (IS_ENABLED(CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE)) - return MAINBOARD_POWER_STATE_PREVIOUS; - else if (IS_ENABLED(CONFIG_POWER_STATE_ON_AFTER_FAILURE)) - return MAINBOARD_POWER_STATE_ON; - - return MAINBOARD_POWER_STATE_OFF; + return CONFIG_MAINBOARD_POWER_FAILURE_STATE; } diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 08ec59f..3250585 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -31,10 +31,6 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - #define BIT0 (1 << 0) #define BIT1 (1 << 1) #define BIT2 (1 << 2) diff --git a/src/southbridge/amd/amd8111/Kconfig b/src/southbridge/amd/amd8111/Kconfig index 1436d8c..9764c95 100644 --- a/src/southbridge/amd/amd8111/Kconfig +++ b/src/southbridge/amd/amd8111/Kconfig @@ -16,6 +16,8 @@ config SOUTHBRIDGE_AMD_AMD8111 bool select IOAPIC + select HAVE_POWER_STATE_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
config BOOTBLOCK_SOUTHBRIDGE_INIT string diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c index 8dc2007..5216a10 100644 --- a/src/southbridge/amd/amd8111/acpi.c +++ b/src/southbridge/amd/amd8111/acpi.c @@ -29,11 +29,6 @@ #define SLOW_CPU_OFF 0 #define SLOW_CPU__ON 1
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - - static int lsmbus_recv_byte(struct device *dev) { unsigned int device; @@ -148,7 +143,7 @@ pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5));
/* power on after power fail */ - on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 3625f8a..5c809d6 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -31,10 +31,6 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* * HUDSON enables all USB controllers by default in SMBUS Control. * HUDSON enables SATA by default in SMBUS Control. diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 6d62e67..78332cf 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -23,6 +23,9 @@ select IOAPIC select HAVE_USBDEBUG_OPTIONS select SMBUS_HAS_AUX_CHANNELS + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI bool "Enable high speed SPI clock" diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 64c6db3..4c3992d 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -44,10 +44,6 @@ POWER_MODE_LAST = 2, };
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL POWER_MODE_ON -#endif - static const char *power_mode_names[] = { [POWER_MODE_OFF] = "off", [POWER_MODE_ON] = "on", @@ -152,11 +148,11 @@ pm_iowrite(0x53, byte);
/* power after power fail */ - power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + power_state = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&power_state, "power_on_after_fail"); if (power_state > 2) { printk(BIOS_WARNING, "Invalid power_on_after_fail setting, using default\n"); - power_state = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + power_state = CONFIG_MAINBOARD_POWER_FAILURE_STATE; } byte = pm_ioread(0x74); byte &= ~0x03; diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index fdb6283..1d2daed8 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -32,10 +32,6 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - #define BIT0 (1 << 0) #define BIT1 (1 << 1) #define BIT2 (1 << 2) diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7ae538e..bee82b9 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -181,7 +181,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option;
/* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 957faa5..951aecb 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -29,6 +29,9 @@
config SOUTHBRIDGE_INTEL_COMMON_SMM def_bool n + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT bool diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index c578982..8b71627 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -35,10 +35,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - #define PM1_STS 0x00 #define WAK_STS (1 << 15) #define PCIEXPWAK_STS (1 << 14) diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 0ad400c..3d51257 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -112,7 +112,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
// save and recover RTC port values u8 tmp70, tmp72; diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig index 52810ab..7445012 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig @@ -33,6 +33,9 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select HAVE_INTEL_CHIPSET_LOCKDOWN + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
config EHCI_BAR hex diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index bc9e06b..fa664ad 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -192,7 +192,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option;
/* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 1f1c18a..bfcb9e9 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -96,10 +96,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index dedc4be..156c3ec 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -306,7 +306,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
// save and recover RTC port values u8 tmp70, tmp72; diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig index 0bc9586..d570068 100644 --- a/src/southbridge/intel/fsp_i89xx/Kconfig +++ b/src/southbridge/intel/fsp_i89xx/Kconfig @@ -33,6 +33,9 @@ select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
config EHCI_BAR hex diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c index 8019b02..d079328 100644 --- a/src/southbridge/intel/fsp_i89xx/lpc.c +++ b/src/southbridge/intel/fsp_i89xx/lpc.c @@ -192,7 +192,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option;
/* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h index 3382cbd..7b96708 100644 --- a/src/southbridge/intel/fsp_i89xx/pch.h +++ b/src/southbridge/intel/fsp_i89xx/pch.h @@ -93,10 +93,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) #define PCH_PCIE_DEV_SLOT 28 diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index e22faad..81fdb43 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -305,7 +305,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
// save and recover RTC port values u8 tmp70, tmp72; diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index ffadee4..9d86407 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -80,10 +80,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - #define SOC_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCIE_DEV_SLOT0 1 #define PCIE_DEV_SLOT1 2 diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 827f6bb..f4357b8 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -22,6 +22,9 @@ select HAVE_USBDEBUG select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
if SOUTHBRIDGE_INTEL_I82801DX
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 8c7da55..678d5d7 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -45,10 +45,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* * 000 = Non-combined. P0 is primary master. P1 is secondary master. * 001 = Non-combined. P0 is secondary master. P1 is primary master. diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 925251d..3c74e98 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -103,7 +103,7 @@ u32 reg32; const char *state;
- int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option;
/* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index b2b4662..e7a9589 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -276,7 +276,7 @@ * CMOS or even better from GNVS. Right now it's hard * coded at compile time. */ - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
/* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN); diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 28d42ff..69cb2e7 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -28,6 +28,9 @@ select HAVE_INTEL_CHIPSET_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select INTEL_HAS_TOP_SWAP + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
if SOUTHBRIDGE_INTEL_I82801GX
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d14a809..828f1a9 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -59,10 +59,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 7dcec50..13ea221 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -172,7 +172,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info;
- int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option;
/* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 3f537c0..92c6384 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -357,7 +357,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
// save and recover RTC port values u8 tmp70, tmp72; diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index aed1999..f094ed8 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -85,11 +85,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - - /* D31:F0 LPC bridge */ #define D31F0_PMBASE 0x40 #define D31F0_ACPI_CNTL 0x44 diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index a69b879..05fbcdc 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -170,7 +170,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option;
/* BIOS must program... */ diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 4308e29..4b523b7 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -29,6 +29,9 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select COMMON_FADT select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
if SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 3c09746..4813dd8 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -76,11 +76,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - - /* D31:F0 LPC bridge */ #define D31F0_PMBASE 0x40 #define PMBASE D31F0_PMBASE diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index ba79e73..250ce08 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -172,7 +172,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option;
/* BIOS must program... */ diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index fe6526d..796e165 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -37,6 +37,9 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select SOUTHBRIDGE_INTEL_COMMON_GPIO select HAVE_INTEL_CHIPSET_LOCKDOWN + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index e5cbc59..a6d1435 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -174,7 +174,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info;
- int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option;
/* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 55478b9..3938662 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -86,10 +86,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index b70273c..125b90a 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -403,7 +403,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
// save and recover RTC port values u8 tmp70, tmp72; diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 5b06c4b..92582e5 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -37,6 +37,9 @@ select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select HAVE_INTEL_CHIPSET_LOCKDOWN select COMMON_FADT + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ca850c0..181a982 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -189,7 +189,7 @@ /* Get the chip configuration */ config_t *config = dev->chip_info; u16 pmbase = get_pmbase(); - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option;
/* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index a02be81..36ef704 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -210,10 +210,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 87848c2..21da3ab 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -107,7 +107,7 @@ u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; u16 pmbase = get_pmbase();
// save and recover RTC port values diff --git a/src/southbridge/nvidia/ck804/Kconfig b/src/southbridge/nvidia/ck804/Kconfig index 338357e..08f213c 100644 --- a/src/southbridge/nvidia/ck804/Kconfig +++ b/src/southbridge/nvidia/ck804/Kconfig @@ -2,6 +2,8 @@ bool select HAVE_USBDEBUG select IOAPIC + select HAVE_POWER_STATE_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
if SOUTHBRIDGE_NVIDIA_CK804
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 2c7519b..fe915ee 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -47,10 +47,6 @@ #define SLOW_CPU_OFF 0 #define SLOW_CPU__ON 1
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - static void lpc_common_init(struct device *dev) { u32 dword; @@ -114,7 +110,7 @@ printk(BIOS_INFO, "%s: pm_base = %x\n", __func__, pm_base);
/* Power after power fail */ - on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x45; diff --git a/src/southbridge/nvidia/mcp55/Kconfig b/src/southbridge/nvidia/mcp55/Kconfig index bb1b7df..66dbc99 100644 --- a/src/southbridge/nvidia/mcp55/Kconfig +++ b/src/southbridge/nvidia/mcp55/Kconfig @@ -2,6 +2,8 @@ bool select HAVE_USBDEBUG select IOAPIC + select HAVE_POWER_STATE_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE
if SOUTHBRIDGE_NVIDIA_MCP55
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 3ac6464..7e0fc89 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -48,10 +48,6 @@ #define SLOW_CPU_OFF 0 #define SLOW_CPU__ON 1
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - static void lpc_common_init(struct device *dev, int master) { u8 byte; @@ -93,7 +89,7 @@ /* power after power fail */
#if 1 - on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; diff --git a/src/superio/nuvoton/nct5572d/Kconfig b/src/superio/nuvoton/nct5572d/Kconfig index b666174..0a29f97 100644 --- a/src/superio/nuvoton/nct5572d/Kconfig +++ b/src/superio/nuvoton/nct5572d/Kconfig @@ -16,3 +16,6 @@ config SUPERIO_NUVOTON_NCT5572D bool select SUPERIO_NUVOTON_COMMON_ROMSTAGE + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 10542d5..2026704 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -28,12 +28,9 @@
#include "nct5572d.h"
-#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2
static void nct5572d_init(struct device *dev) { @@ -68,16 +65,16 @@ break; case NCT5572D_ACPI: /* Set power state after power fail */ - power_status = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + power_status = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&power_status, "power_on_after_fail"); pnp_enter_conf_mode_8787(dev); pnp_set_logical_device(dev); byte = pnp_read_config(dev, 0xe4); byte &= ~0x60; - if (power_status == 1) - byte |= (0x1 << 5); /* Force power on */ - else if (power_status == 2) - byte |= (0x2 << 5); /* Use last power state */ + if (power_status == MAINBOARD_POWER_ON) + byte |= (0x1 << 5); + else if (power_status == MAINBOARD_POWER_KEEP) + byte |= (0x2 << 5); pnp_write_config(dev, 0xe4, byte); pnp_exit_conf_mode_aa(dev); printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off"); diff --git a/src/superio/winbond/w83667hg-a/Kconfig b/src/superio/winbond/w83667hg-a/Kconfig index 74b78c2..6274947 100644 --- a/src/superio/winbond/w83667hg-a/Kconfig +++ b/src/superio/winbond/w83667hg-a/Kconfig @@ -17,3 +17,6 @@ config SUPERIO_WINBOND_W83667HG_A bool select SUPERIO_WINBOND_COMMON_ROMSTAGE + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE + select POWER_STATE_DEFAULT_OFF_AFTER_FAILURE diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index ceb783d..eabbd67 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -28,12 +28,9 @@
#include "w83667hg-a.h"
-#define MAINBOARD_POWER_OFF 0 -#define MAINBOARD_POWER_ON 1 - -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2
static void w83667hg_a_init(struct device *dev) { @@ -68,16 +65,16 @@ break; case W83667HG_A_ACPI: /* Set power state after power fail */ - power_status = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + power_status = CONFIG_MAINBOARD_POWER_FAILURE_STATE; get_option(&power_status, "power_on_after_fail"); pnp_enter_conf_mode_8787(dev); pnp_set_logical_device(dev); byte = pnp_read_config(dev, 0xe4); byte &= ~0x60; - if (power_status == 1) - byte |= (0x1 << 5); /* Force power on */ - else if (power_status == 2) - byte |= (0x2 << 5); /* Use last power state */ + if (power_status == MAINBOARD_POWER_ON) + byte |= (0x1 << 5); + else if (power_status == MAINBOARD_POWER_KEEP) + byte |= (0x2 << 5); pnp_write_config(dev, 0xe4, byte); pnp_exit_conf_mode_aa(dev); printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off");
-
Nico Huber (Code Review)