[XS] Change in coreboot[master]: nb/intel/haswell: Correct PCI bus range at runtime

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76199?usp=email )

Change subject: nb/intel/haswell: Correct PCI bus range at runtime
......................................................................

nb/intel/haswell: Correct PCI bus range at runtime

ECAM_MMCONF_BUS_NUMBER defaults to 64 for Haswell, but the ASL code
sets the maximum of 256 buses. Patch the resource so that the actual
number as set in Kconfig is used.

Change-Id: I492c5a4336dcd0e7e4964f3f5e2bb53ffe05721f
Signed-off-by: Nico Huber 
---
M src/northbridge/intel/haswell/acpi/hostbridge.asl
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/76199/1

diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 513e960..22b8f1c 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -140,6 +140,12 @@

Method (_CRS, 0, Serialized)
 {
+	/* Set highest PCI bus and length */
+	CreateWordField(MCRS, ^PB00._MAX, BMAX)
+	CreateWordField(MCRS, ^PB00._LEN, BLEN)
+	BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
+	BMAX = BLEN - 1
+
    // Find PCI resource area in MCRS
    CreateDwordField (MCRS, ^PM01._MIN, PMIN)
    CreateDwordField (MCRS, ^PM01._MAX, PMAX)