Change in coreboot[master]: [WIP] soc/amd/cezanne,common,picasso: use BERT region reserved by FSP...

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52584 )

Change subject: [WIP] soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver
......................................................................

[WIP] soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver

commit ce0e2a014009390c4527e064efb59260ef4d3a3b (drivers/intel/fsp2_0:
use FSP to allocate APEI BERT memory region) adds a mechanism to reserve
the BERT region inside the coreboot code, so we can get rid of the
workaround to reserve it in the FSP and return the location in a HOB.
mcfg->bert_size defaults to 0 which makes the FSP not generate the
corresponding HOB, but that field is planned to be removed at least on
Cezanne, so don't explicitly set it to 0.

TODO: test if Linux likes this or not

BUG=b:169934025

Signed-off-by: Felix Held 
Change-Id: Iaca89b47793bf9982181560f026459a18e7db134
---
M src/soc/amd/cezanne/fsp_m_params.c
M src/soc/amd/common/block/cpu/noncar/memmap.c
M src/soc/amd/picasso/fsp_m_params.c
M src/vendorcode/amd/fsp/cezanne/FspGuids.h
M src/vendorcode/amd/fsp/picasso/FspGuids.h
5 files changed, 4 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/52584/1

diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index 9d4159d..b90147f 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -59,7 +59,6 @@

mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
    mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
-	mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
    mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
    mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
    mcfg->serial_port_baudrate = get_uart_baudrate();
diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c
index 6ec437c..1cfe848 100644
--- a/src/soc/amd/common/block/cpu/noncar/memmap.c
+++ b/src/soc/amd/common/block/cpu/noncar/memmap.c
@@ -10,6 +10,7 @@
 #include <fsp/util.h>
 #include <FspGuids.h>
 #include <memrange.h>
+#include <string.h>
 #include <types.h>

void memmap_stash_early_dram_usage(void)
@@ -62,19 +63,7 @@

void bert_reserved_region(void **start, size_t *size)
 {
-	struct range_entry bert;
-	int status;
-
-	*start = NULL;
-	*size = 0;
-
-	status = fsp_find_range_hob(&bert, AMD_FSP_BERT_HOB_GUID.b);
-
-	if (status < 0) {
-		printk(BIOS_ERR, "Error: unable to find BERT HOB\n");
-		return;
-	}
-
-	*start = (void *)(uintptr_t)range_entry_base(&bert);
-	*size = range_entry_size(&bert);
+	*start = cbmem_top();
+	*size = CONFIG_ACPI_BERT_SIZE;
+	printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%lx\n", *start, *size);
 }
diff --git a/src/soc/amd/picasso/fsp_m_params.c b/src/soc/amd/picasso/fsp_m_params.c
index fea16cd..5d61d7c 100644
--- a/src/soc/amd/picasso/fsp_m_params.c
+++ b/src/soc/amd/picasso/fsp_m_params.c
@@ -68,7 +68,6 @@

mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
    mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
-	mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
    mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
    mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
    mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1;
diff --git a/src/vendorcode/amd/fsp/cezanne/FspGuids.h b/src/vendorcode/amd/fsp/cezanne/FspGuids.h
index 7f7a91d..69cb8b7 100644
--- a/src/vendorcode/amd/fsp/cezanne/FspGuids.h
+++ b/src/vendorcode/amd/fsp/cezanne/FspGuids.h
@@ -9,8 +9,4 @@
    	GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \
    	0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c)

-#define AMD_FSP_BERT_HOB_GUID \
-		GUID_INIT(0xa21f7ab5, 0x6a89, 0x4df2, \
-		0xb9, 0x19, 0x51, 0xad, 0x95, 0x50, 0x5b, 0xd8)
-
 #endif /* __FSP_GUIDS__ */
diff --git a/src/vendorcode/amd/fsp/picasso/FspGuids.h b/src/vendorcode/amd/fsp/picasso/FspGuids.h
index 70bbe74..64bf97c 100644
--- a/src/vendorcode/amd/fsp/picasso/FspGuids.h
+++ b/src/vendorcode/amd/fsp/picasso/FspGuids.h
@@ -9,10 +9,6 @@
    	GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \
    	0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c)

-#define AMD_FSP_BERT_HOB_GUID \
-		GUID_INIT(0xa21f7ab5, 0x6a89, 0x4df2, \
-		0xb9, 0x19, 0x51, 0xad, 0x95, 0x50, 0x5b, 0xd8)
-
 #define AMD_FSP_ACPI_SSDT_HOB_GUID \
    	GUID_INIT(0x54445353, 0x4002, 0x403b, \
    	0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A)