Change in coreboot[master]: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths - coreboot-gerrit

9 Sep 2020


      Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44557 )
Change subject: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths
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Patch Set 2: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f
Gerrit-Change-Number: 44557
Gerrit-PatchSet: 2
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Gerrit-Comment-Date: Wed, 09 Sep 2020 18:45:18 +0000
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