Attention is currently required from: Tarun Tuli.
Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69755 )
Change subject: [DONOTMERGE] brya/skolas: graphic configuration ......................................................................
[DONOTMERGE] brya/skolas: graphic configuration
Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com Change-Id: Iddc2d9b2fe3dc15a4f6706e90db6268ce4ce2043 --- M src/drivers/intel/gma/Kconfig M src/mainboard/google/brya/Makefile.inc A src/mainboard/google/brya/gma-mainboard.ads M src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb 4 files changed, 42 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/69755/1
diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 87f6d12..d0aff4c 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -86,7 +86,7 @@ || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL \ || SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_APOLLOLAKE \ - || SOC_INTEL_CANNONLAKE_BASE + || SOC_INTEL_CANNONLAKE_BASE || SOC_INTEL_ALDERLAKE depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID select RAMSTAGE_LIBHWBASE
@@ -125,6 +125,7 @@ default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X + default "Tigerlake" if SOC_INTEL_ALDERLAKE
config GFX_GMA_PCH string @@ -133,6 +134,7 @@ default "Lynx_Point" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL default "Sunrise_Point" if SOC_INTEL_COMMON_SKYLAKE_BASE default "Cannon_Point" if SOC_INTEL_CANNONLAKE_BASE + default "Alder_Point" if SOC_INTEL_ALDERLAKE default "No_PCH"
config GFX_GMA_PANEL_1_PORT diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc index c40f21c..98a08f2 100644 --- a/src/mainboard/google/brya/Makefile.inc +++ b/src/mainboard/google/brya/Makefile.inc @@ -20,3 +20,4 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads \ No newline at end of file diff --git a/src/mainboard/google/brya/gma-mainboard.ads b/src/mainboard/google/brya/gma-mainboard.ads new file mode 100644 index 0000000..a7023d5 --- /dev/null +++ b/src/mainboard/google/brya/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; +private package GMA.Mainboard is + + + -- NOTE: your board probably doesn’t have ALL of these + -- outputs; only list the ones your board actually has here. + ports : constant Port_List := + (eDP, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb index c861c9b..485ea90 100644 --- a/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/skolas/devicetree.cb @@ -127,7 +127,17 @@ }"
device domain 0 on - device ref igpu on end + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + # Power Sequence: T3 2000 T7 10 T9 2000 T10 500 T12 5000 + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200,}" + end device ref dtt on end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end
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Jérémy Compostella (Code Review)