[M] Change in coreboot[main]: mb/google/fatcat: Remove chromeos-debug-fsp.fmd

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85971?usp=email )

Change subject: mb/google/fatcat: Remove chromeos-debug-fsp.fmd
......................................................................

mb/google/fatcat: Remove chromeos-debug-fsp.fmd

The file chromeos-debug-fsp.fmd is no longer needed, as the FMD
configuration is now handled by the generic Chrome OS FMD file.

This change removes the file to simplify the build process and
reduce the amount of code that needs to be maintained.

Change-Id: Ida430d415ae3f7dc93b89eb4d7c7ba59ed280e1b
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/fatcat/Kconfig
D src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
2 files changed, 0 insertions(+), 53 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/85971/1

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 37ba330..73d6b2a 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -117,10 +117,6 @@
    default 0x03 if BOARD_GOOGLE_MODEL_FATCAT
    default 0x01 if BOARD_GOOGLE_FRANCKA

-config FMDFILE
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP
-	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
-
 config HAVE_SLP_S0_GATE
    def_bool n

diff --git a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
deleted file mode 100644
index 0e1e636..0000000
--- a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd
+++ /dev/null
@@ -1,49 +0,0 @@
-FLASH 32M {
-	SI_ALL 8M {
-		SI_DESC 16K
-		SI_ME
-	}
-	SI_BIOS 24M {
-		RW_SECTION_A 7680K {
-			VBLOCK_A 8K
-			FW_MAIN_A(CBFS)
-			RW_FWID_A 64
-		}
-		RW_MISC 1M {
-			UNIFIED_MRC_CACHE(PRESERVE) 128K {
-				RECOVERY_MRC_CACHE 64K
-				RW_MRC_CACHE 64K
-			}
-			RW_ELOG(PRESERVE) 16K
-			RW_SHARED 16K {
-				SHARED_DATA 8K
-				VBLOCK_DEV 8K
-			}
-			RW_VPD(PRESERVE) 8K
-			RW_NVRAM(PRESERVE) 24K
-		}
-		# This section starts at the 16M boundary in SPI flash.
-		# PTL does not support a region crossing this boundary,
-		# because the SPI flash is memory-mapped into two non-
-		# contiguous windows.
-		RW_SECTION_B 7680K {
-			VBLOCK_B 8K
-			FW_MAIN_B(CBFS)
-			RW_FWID_B 64
-		}
-		RW_LEGACY(CBFS) 1M
-		RW_UNUSED 3M
-		# Make WP_RO region align with SPI vendor
-		# memory protected range specification.
-		WP_RO 4M {
-			RO_VPD(PRESERVE) 16K
-			RO_GSCVD 8K
-			RO_SECTION {
-				FMAP 2K
-				RO_FRID 64
-				GBB@4K 12K
-				COREBOOT(CBFS)
-			}
-		}
-	}
-}