New patch to review for coreboot: AMD Bettong: add memory configuration for DDR3 and DDR4
WANG Siyuan (wangsiyuanbuaa@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11733
-gerrit
commit d49159f819ece1b51be6fca89ea4043de6705083 Author: WANG Siyuan wangsiyuanbuaa@gmail.com Date: Fri Jul 3 22:15:31 2015 +0800
AMD Bettong: add memory configuration for DDR3 and DDR4
1. Bettong Rev A-E are DDR3, Bettong Rev F is DDR4. Rev F's SPD address is different from DDR3.
0 1 Channel A A0 A2 Channel B A4 AC
2. DDR4 uses different memory configuration in AGESA. Pass memory configuration parameters in agesawrapper_amdinitpost.
3. Tested on Rev C and Rev F. Both of them can boot to Windows 8 and have the correct memory size.
Change-Id: Ia0d35ebf1b65c399abc3777ee6bdb107437a4345 Signed-off-by: WANG Siyuan wangsiyuanbuaa@gmail.com Signed-off-by: WANG Siyuan SiYuan.Wang@amd.com --- src/northbridge/amd/pi/00660F01/dimmSpd.c | 19 ++++++++++++++++- src/northbridge/amd/pi/agesawrapper.c | 35 +++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c index 6996f83..0244f3e 100644 --- a/src/northbridge/amd/pi/00660F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c @@ -20,6 +20,7 @@ #include <device/pci_def.h> #include <device/device.h> #include <stdlib.h> +#include <string.h>
/* warning: Porting.h includes an open #pragma pack(1) */ #include "Porting.h" @@ -27,12 +28,28 @@ #include "amdlib.h" #include "chip.h" #include "northbridge/amd/pi/dimmSpd.h" +#if IS_ENABLED(CONFIG_BOARD_AMD_BETTONG) +#include "board_rev.h" +#endif
AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) { int spdAddress; ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); - ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info; + struct northbridge_amd_pi_00660F01_config *config, user_config; + memcpy(&user_config, dev->chip_info, sizeof(user_config)); + +#if IS_ENABLED(CONFIG_BOARD_AMD_BETTONG) + char boardid = get_board_id(); + if (boardid == 'F') { + user_config.spdAddrLookup[0][0][0] = 0xA0; + user_config.spdAddrLookup[0][0][1] = 0xA2; + user_config.spdAddrLookup[0][1][0] = 0xA4; + user_config.spdAddrLookup[0][1][1] = 0xAC; + } +#endif + + config = &user_config;
if ((dev == 0) || (config == 0)) return AGESA_ERROR; diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 9bdf340..8a72660 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -26,6 +26,10 @@ #include <heapManager.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/BiosCallOuts.h> +#include <PlatformMemoryConfiguration.h> +#if IS_ENABLED(CONFIG_BOARD_AMD_BETTONG) +#include "board_rev.h" +#endif
VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); @@ -136,6 +140,37 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr;
+ PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + MOTHER_BOARD_LAYERS (LAYERS_6), + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + PSO_END + }; + + PSO_ENTRY DDR3PlatformMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR3_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + MOTHER_BOARD_LAYERS (LAYERS_6), + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff), + CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00), + PSO_END + }; + +#if IS_ENABLED(CONFIG_BOARD_AMD_BETTONG) + char boardid = get_board_id(); + if (boardid == 'F') + PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; + else + PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR3PlatformMemoryConfiguration; +#endif // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG_GFXUMA ? UMA_AUTO : UMA_NONE;
-
WANG Siyuan