Change in coreboot[master]: [TESTME] nb/intel/ironlake: Improve late quickpath init

[Angel Pons (Code Review)]

Attention is currently required from: Patrick Rudolph.
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60222 )

Change subject: [TESTME] nb/intel/ironlake: Improve late quickpath init
......................................................................

[TESTME] nb/intel/ironlake: Improve late quickpath init

Change-Id: Ib7dddf3d1078a1d99c5a140793b9fdffdd73c14c
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/ironlake/quickpath.c
1 file changed, 78 insertions(+), 28 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/60222/1

diff --git a/src/northbridge/intel/ironlake/quickpath.c b/src/northbridge/intel/ironlake/quickpath.c
index e13f93f..5e04c9c 100644
--- a/src/northbridge/intel/ironlake/quickpath.c
+++ b/src/northbridge/intel/ironlake/quickpath.c
@@ -589,9 +589,33 @@
    mchbar_write32(0x18ac, 0x22222);
 }

+static u16 get_1122_value(const struct raminfo *info, const bool is_mobile_si)
+{
+	if (info->revision < 0x8) {
+		switch (info->clock_speed_index) {
+		case 0:
+			return 0x3313;
+		case 1:
+			return 0x3011;
+		case 2:
+			return 0x2f0f;
+		}
+	} else if (!is_mobile_si) {
+		switch (info->clock_speed_index) {
+		case 0:
+			return 0x321a;
+		case 1:
+			return 0x2e16;
+		case 2:
+			return 0x2b13;
+		}
+	}
+	return 0x220a;
+}
+
 void late_quickpath_init(struct raminfo *info, const int s3resume)
 {
-	const u16 deven = pci_read_config16(NORTHBRIDGE, DEVEN);
+	const bool is_mobile_si = info->silicon_revision == 2 || info->silicon_revision == 3;

if (s3resume && info->cached_training) {
    	program_274265(info->cached_training);
@@ -602,15 +626,15 @@

set_2dxx_series(info, s3resume);

-	if (!(deven & 8)) {
-		mchbar_clrsetbits32(0x2cb0, ~0, 0x40);
+	if ((pci_read_config32(NORTHBRIDGE, CAPID0 + 4) >> 11) & 1) {
+		mchbar_setbits32(0x2cb0, 0x1c0);
    }

-	udelay(1000);
-
-	if (deven & 8) {
-		mchbar_setbits32(0xff8, 3 << 11);
-		mchbar_clrbits32(0x2cb0, ~0);
+	if (!info->uma_enabled) {
+		mchbar_setbits32(0x2cb0, 0x40);
+	} else {
+		mchbar_setbits32(0xff8, 1 << 11 | (1 + info->revision < 0x8) << 12);
+		mchbar_clrbits32(0x2cb0, 0x1c0);
    	pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
    	pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
    	pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e);
@@ -667,18 +691,35 @@
    	mchbar_write32(0x1140, 0x54942404);
    	mchbar_write32(0x1190, 0x900080a);
    	mchbar_write16(0x11c0, 0xc40b);
-		mchbar_write16(0x11c2, 0x303);
-		mchbar_write16(0x11c4, 0x301);
-		mchbar_clrsetbits32(0x1190, ~0, 0x8900080a);
-		mchbar_write32(0x11b8, 0x70c3000);
-		mchbar_write8(0x11ec, 0xa);
-		mchbar_write16(0x1100, 0x800);
-		mchbar_clrsetbits32(0x11bc, ~0, 0x1e84800);
-		mchbar_write16(0x11ca, 0xfa);
-		mchbar_write32(0x11e4, 0x4e20);
-		mchbar_write8(0x11bc, 0xf);
-		mchbar_write16(0x11da, 0x19);
-		mchbar_write16(0x11ba, 0x470c);
+		if (is_mobile_si) {
+			mchbar_write16(0x11c2, 0x303);
+			mchbar_write16(0x11c4, 0x301 | (info->revision < 0x8) << 1);
+		} else {
+			mchbar_write16(0x11c2, 0x606);
+			mchbar_write16(0x11c4, 0x606);
+		}
+		if (info->silicon_revision == 3)
+			mchbar_setbits32(0x1190, 1 << 31);
+
+		if (is_mobile_si) {
+			mchbar_write32(0x11b8, 0x70c3000);
+			mchbar_write8(0x11ec, 0xa);
+			mchbar_write16(0x1100, info->revision < 0x8 ? 0x3f00 : 0x800);
+			mchbar_clrsetbits32(0x11bc, 0xffffff << 8, 0x1e848 << 8);
+			mchbar_write16(0x11ca, 0xfa);
+			mchbar_write32(0x11e4, 0x4e20);
+			mchbar_write8(0x11bc, 0xf);
+			mchbar_write16(0x11da, 0x19);
+			mchbar_write16(0x11ba, 0x470c);
+		} else {
+			mchbar_write32(0x11b8, 0x5040800);
+			mchbar_write8(0x11ec, 0xa);
+			mchbar_write16(0x1100, info->revision < 0x8 ? 0x3600 : 0x2600);
+			mchbar_clrsetbits32(0x11bc, 0xffffff << 8, 0x186a0 << 8);
+			mchbar_write16(0x11ca, 0xc8);
+			mchbar_write32(0x11e4, 0x7d0);
+			mchbar_write16(0x11ba, 0x4504);
+		}
    	mchbar_write32(0x1680, 0xe6ffe4ff);
    	mchbar_write32(0x1684, 0xdeffdaff);
    	mchbar_write32(0x1688, 0xd4ffd0ff);
@@ -690,11 +731,19 @@
    	mchbar_write32(0x1290, 0x5000000);
    }

-	mchbar_write32(0x124c, 0x15040d00);
-	mchbar_write32(0x1250, 0x7f0000);
-	mchbar_write32(0x1254, 0x1e220004);
-	mchbar_write32(0x1258, 0x4000004);
-	mchbar_write32(0x1278, 0x0);
+	if (info->revision < 0x10) {
+		mchbar_write32(0x1250, 0xff3d0000);
+		mchbar_write32(0x1254, 0x0);
+		mchbar_write32(0x1258, 0x60001);
+		mchbar_write32(0x1278, 0x1000001);
+		mchbar_write32(0x124c, 0x8070800);
+	} else {
+		mchbar_write32(0x124c, 0x15040d00);
+		mchbar_write32(0x1250, 0x7f0000);
+		mchbar_write32(0x1254, 0x1e220004);
+		mchbar_write32(0x1258, 0x4000004);
+		mchbar_write32(0x1278, 0x0);
+	}
    mchbar_write32(0x125c, 0x0);
    mchbar_write32(0x1260, 0x0);
    mchbar_write32(0x1264, 0x0);
@@ -703,7 +752,7 @@
    mchbar_write32(0x1270, 0x0);
    mchbar_write32(0x1274, 0x0);

-	if (deven & 8) {
+	if (info->uma_enabled) {
    	mchbar_write16(0x1214, 0x320);
    	mchbar_write32(0x1600, 0x40000000);
    	mchbar_clrsetbits32(0x11f4, ~0, 1 << 28);
@@ -799,8 +848,9 @@
    	mchbar_write32(0x1560, 0x4051210);
    	mchbar_write32(0x1564, 0x1010001);
    	mchbar_write32(0x1568, 0x1110000);
-		mchbar_write16(0x1222, 0x220a);
-		mchbar_write16(0x123c, 0x1fc0);
+		mchbar_write16(0x1222, get_1122_value(info, is_mobile_si));
+		if (info->revision >= 0x8)
+			mchbar_write16(0x123c, 0x1fc0);
    	mchbar_write16(0x1220, 0x1388);
    }
 }