[XS] Change in coreboot[master]: mb/google/rex/var/screebo: set HBR smbus pin as NC

[Simon Zhou (Code Review)]

Simon Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75643?usp=email )

Change subject: mb/google/rex/var/screebo: set HBR smbus pin as NC
......................................................................

mb/google/rex/var/screebo: set HBR smbus pin as NC

Since GPP_C03/GPP_04 are floating in HW design, we set HBR smbus pin
as NC, in case block ese and cse are blocked from  entering suspend.

BUG=b:283053968
TEST=Verified on screebo non-TBT SKU, suspend and resume works.

Change-Id: I401db32f0286de61ce3ab6c61de9528ec76cb51d
---
M src/mainboard/google/rex/variants/screebo/gpio.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/75643/1

diff --git a/src/mainboard/google/rex/variants/screebo/gpio.c b/src/mainboard/google/rex/variants/screebo/gpio.c
index f31506c..cf867b0 100644
--- a/src/mainboard/google/rex/variants/screebo/gpio.c
+++ b/src/mainboard/google/rex/variants/screebo/gpio.c
@@ -94,9 +94,9 @@
    /* GPP_C02 : SOC_TCHSCR_SPI_INT_STRAP ==> Component NC */
    PAD_NC(GPP_C02, NONE),
    /* GPP_C03 : [] ==> SOC_TCP_SMBUS_CLK*/
-	PAD_CFG_NF_LOCK(GPP_C03, NONE, NF1, LOCK_CONFIG),
+	PAD_NC(GPP_C03, NONE),
    /* GPP_C04 : [] ==> SOC_TCP_SMBUS_SDA*/
-	PAD_CFG_NF_LOCK(GPP_C04, NONE, NF1, LOCK_CONFIG),
+	PAD_NC(GPP_C04, NONE),
    /* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */
    PAD_NC(GPP_C05, NONE),
    /* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */