Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32267
Change subject: mb/asrock/h110m: Add virtual LDN for SurerIO to DT ......................................................................
mb/asrock/h110m: Add virtual LDN for SurerIO to DT
Adds virtual logical devices numbers for the Nuvoton (NCT6791D) SuperIO to the devicetree.
Change-Id: I7df1633951c30fef14c62c89aaedebd3044b312f Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 19 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32267/1
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index e13076e..158801f 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -344,11 +344,18 @@ irq 0x72 = 12 # Mouse end device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6..8 - # WDT1, WDT_MEM, GPIO 0, GPIO 1 - device pnp 2e.8 off end - # GPIO 2, GPIO 3, GPIO 4, GPIO 5 - device pnp 2e.9 off end + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 device pnp 2e.a off end # ACPI device pnp 2e.b on # HWM, LED io 0x60 = 0x0290 @@ -359,7 +366,13 @@ device pnp 2e.e off end # CIR wake-up device pnp 2e.f off end # GPIO PP/OD device pnp 2e.14 off end # SVID, Port 80 UART - device pnp 2e.16 off end # Deep sleep + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 off end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU end # superio/nuvoton/nct6791d chip drivers/pc80/tpm device pnp 4e.0 on end # TPM module
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32267
to look at the new patch set (#2).
Change subject: mb/asrock/h110m: Add virtual LDN for SurerIO to DT ......................................................................
mb/asrock/h110m: Add virtual LDN for SurerIO to DT
Adds virtual logical devices numbers for the Nuvoton (NCT6791D) SuperIO to the devicetree.
Change-Id: I7df1633951c30fef14c62c89aaedebd3044b312f Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 19 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32267/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32267 )
Change subject: mb/asrock/h110m: Add virtual LDN for SurerIO to DT ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32267 )
Change subject: mb/asrock/h110m: Add virtual LDN for SurerIO to DT ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Tiny typo in the commit message, looks reasonable otherwise
https://review.coreboot.org/#/c/32267/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32267/2//COMMIT_MSG@7 PS2, Line 7: SurerIO SuperIO
Hello Patrick Rudolph, Felix Held, Angel Pons, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32267
to look at the new patch set (#3).
Change subject: mb/asrock/h110m: Add virtual LDN for SuperIO to DT ......................................................................
mb/asrock/h110m: Add virtual LDN for SuperIO to DT
Adds virtual logical devices numbers for the Nuvoton (NCT6791D) SuperIO to the devicetree.
Change-Id: I7df1633951c30fef14c62c89aaedebd3044b312f Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 19 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32267/3
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32267 )
Change subject: mb/asrock/h110m: Add virtual LDN for SuperIO to DT ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32267/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32267/2//COMMIT_MSG@7 PS2, Line 7: SurerIO
SuperIO
Sorry) I fixed it
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32267 )
Change subject: mb/asrock/h110m: Add virtual LDN for SuperIO to DT ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/32267/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32267/2//COMMIT_MSG@7 PS2, Line 7: SurerIO
Sorry) […]
Nice, thanks.
BTW, Gerrit has a built-in editor for the commit message :)
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32267 )
Change subject: mb/asrock/h110m: Add virtual LDN for SuperIO to DT ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32267/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32267/2//COMMIT_MSG@7 PS2, Line 7: SurerIO
Nice, thanks. […]
Well, I will use it next time :) Thanks
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32267 )
Change subject: mb/asrock/h110m: Add virtual LDN for SuperIO to DT ......................................................................
mb/asrock/h110m: Add virtual LDN for SuperIO to DT
Adds virtual logical devices numbers for the Nuvoton (NCT6791D) SuperIO to the devicetree.
Change-Id: I7df1633951c30fef14c62c89aaedebd3044b312f Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32267 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 19 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index e13076e..158801f 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -344,11 +344,18 @@ irq 0x72 = 12 # Mouse end device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6..8 - # WDT1, WDT_MEM, GPIO 0, GPIO 1 - device pnp 2e.8 off end - # GPIO 2, GPIO 3, GPIO 4, GPIO 5 - device pnp 2e.9 off end + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 device pnp 2e.a off end # ACPI device pnp 2e.b on # HWM, LED io 0x60 = 0x0290 @@ -359,7 +366,13 @@ device pnp 2e.e off end # CIR wake-up device pnp 2e.f off end # GPIO PP/OD device pnp 2e.14 off end # SVID, Port 80 UART - device pnp 2e.16 off end # Deep sleep + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 off end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU end # superio/nuvoton/nct6791d chip drivers/pc80/tpm device pnp 4e.0 on end # TPM module
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Angel Pons (Code Review) -
Felix Held (Code Review)
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Maxim Polyakov (Code Review)
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Patrick Georgi (Code Review)