[S] Change in coreboot[main]: treewide: Rename PM4LE -> PML4E

[Maximilian Brune (Code Review)]

Attention is currently required from: Felix Held, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Jérémy Compostella, Matt DeVillier.

Hello Felix Held, Fred Reitberger, Intel coreboot Reviewers, Jason Glenesk, Jérémy Compostella, Matt DeVillier,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86587?usp=email

to look at the new patch set (#2).

Change subject: treewide: Rename PM4LE -> PML4E
......................................................................

treewide: Rename PM4LE -> PML4E

The x86 (AMD and Intel) spec defines it as Page-Map Level-4 Entry.
It is annoying when searching for the wrong abbreviation in the spec so
fix it everywhere it occurs.

source: Intel 64 spec April 2022 and AMD64 spec April 2024.

Signed-off-by: Maximilian Brune 
Change-Id: I730235beea69b3720f080bbade083c2eeed26587
---
M payloads/libpayload/arch/x86/head_64.S
M payloads/libpayload/arch/x86/pt.S
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/x86/64bit/mode_switch2.S
M src/cpu/x86/64bit/pt.S
M src/cpu/x86/64bit/pt1G.S
M src/cpu/x86/smm/smm_module_loader.c
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
12 files changed, 22 insertions(+), 22 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/86587/2