[S] Change in coreboot[master]: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Tim Van Patten.

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74378 )

Change subject: vc/amd/fsp/phoenix/platform_descriptors: add PCIe gen 4 link speed
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Patch Set 1:

(1 comment)

Patchset:

PS1:
> Oh, nice. I'm glad it was this easy. […]

this at least corresponds to what i saw in the reference code. not sure if any work is needed on the fsp side or if everything is already in place there. the reference code also sets in the pspp related port parameters in the equivalent of the port descriptor struct array, but i'd advise against enabling pspp too early; iirc on cezanne enabling pspp caused a bit of trouble at first, so it's not a too great idea to already enable pspp for bringup