Change in coreboot[master]: soc/intel/elkhartlake: Enable PCH GBE

[Werner Zeh (Code Review)]

Attention is currently required from: Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Lean Sheng Tan, Patrick Rudolph.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55355 )

Change subject: soc/intel/elkhartlake: Enable PCH GBE
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Patch Set 3:

(2 comments)

File src/soc/intel/elkhartlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/55355/comment/058633b1_3631a8e7 
PS3, Line 383: printk(BIOS_ERROR, "ERROR: Unsupported CPU XTAL for GBE config.\n
             : 			Disabling PCH GBE.\n");
             : 			params->PchTsnEnable = 0;
             : 		break;
Please take care of the indention and the missing curly bracket for case-switch.
Further: BIOS_ERR as the printk-level and if you have to split the string among two lines please end every line with a closing  double quote so that the string is complete.

https://review.coreboot.org/c/coreboot/+/55355/comment/477f129d_b31a7d3a 
PS3, Line 375: switch (CONFIG_CPU_XTAL_HZ) {
             : 		case 24000000:
             : 			params->PchTsnGbeLinkSpeed = config->PchTsnGbeLinkSpeed;
             : 			break;
             : 		case 38400000:
             : 			params->PchTsnGbeLinkSpeed = (config->PchTsnGbeLinkSpeed) + 2;
             : 			break;
             : 		default:
             : 		printk(BIOS_ERROR, "ERROR: Unsupported CPU XTAL for GBE config.\n
             : 			Disabling PCH GBE.\n");
             : 			params->PchTsnEnable = 0;
             : 		break;
For now CONFIG_CPU_XTAL_HZ is hard coded in Kconfig of the soc:
config CPU_XTAL_HZ
        default 38400000

When do you expect it to be changed? It would need a patch in this case then.
Is this a mainboard-specific config depending on the used crystal on the mainboard? Or is it something fixed for EHL? In the latter case you can get rid of a few lines here.