Change in coreboot[master]: [TEST] intel/broadwell: Implement proper backlight PWM config
Hello Matt DeVillier,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/35897
to review the following change.
Change subject: [TEST] intel/broadwell: Implement proper backlight PWM config ......................................................................
[TEST] intel/broadwell: Implement proper backlight PWM config
Port the backlight-PWM handling from Skylake instead of the previously used Haswell version.
Lynx Point, the PCH for Haswell and Broadwell, is a transition point for the backlight-PWM config. On platforms with a PCH, we have:
o Before Lynx Point: The CPU has no PWM pin and sends the PWM duty-cycle setting to the PCH. The PCH can choose to ignore that and use its own setting (BLM_PCH_OVERRIDE_ENABLE). We use the CPU setting on these platforms. o Lynx Point + Haswell: The CPU has an additional PWM pin but can be set up to send its setting to the PCH as before. The PCH can still choose to ignore that. We use the CPU setting with Haswell. o Lynx Point + Broadwell: The CPU can't send its setting to the PCH anymore. BLM_PCH_ OVERRIDE_ENABLE must always be set! if the PCH PWM pin is used (it virtually always is). We have to use the PCH setting in this case. o After Lynx Point: Same as with Broadwell, only BLM_PCH_OVERRIDE_ENABLE is implied and the bit not implemented anymore.
TOTEST: Boot Linux with `drm.debug=0xe` with and without this patch, check if it reports the same PWM frequency.
Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/google/auron/variants/auron_paine/devicetree.cb M src/mainboard/google/auron/variants/auron_yuna/devicetree.cb M src/mainboard/google/auron/variants/buddy/devicetree.cb M src/mainboard/google/auron/variants/gandof/devicetree.cb M src/mainboard/google/auron/variants/lulu/devicetree.cb M src/mainboard/google/auron/variants/samus/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/igd.c 10 files changed, 49 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35897/1
diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb index b31d829..5a4fbe1 100644 --- a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb index 3c00ec9..8aeb6d5 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/buddy/devicetree.cb b/src/mainboard/google/auron/variants/buddy/devicetree.cb index f75da84..b322c0c 100644 --- a/src/mainboard/google/auron/variants/buddy/devicetree.cb +++ b/src/mainboard/google/auron/variants/buddy/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb index 118e646..15e9c24 100644 --- a/src/mainboard/google/auron/variants/gandof/devicetree.cb +++ b/src/mainboard/google/auron/variants/gandof/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb index 622ea34..2ac9d50 100644 --- a/src/mainboard/google/auron/variants/lulu/devicetree.cb +++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb index a6c2fea..9e0919b 100644 --- a/src/mainboard/google/auron/variants/samus/devicetree.cb +++ b/src/mainboard/google/auron/variants/samus/devicetree.cb @@ -9,9 +9,8 @@ # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb index e713cd2..176b165 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb @@ -6,9 +6,8 @@ # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb index 3e83d3f..358eca0 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb @@ -6,9 +6,8 @@ # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "183"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 456a435..18a6585 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -117,8 +117,11 @@ u16 gpu_panel_power_backlight_off_delay;
/* Panel backlight settings */ - u32 gpu_cpu_backlight; - u32 gpu_pch_backlight; + unsigned int gpu_pch_backlight_pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } gpu_pch_backlight_polarity;
/* * Graphics CD Clock Frequency diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index dab2d15..f4322bf 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -335,14 +335,34 @@ gtt_write(PCH_PP_DIVISOR, reg32); }
- /* Enable Backlight if needed */ - if (conf->gpu_cpu_backlight) { - gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); - gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); - } - if (conf->gpu_pch_backlight) { - gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); - gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); + /* So far all devices seem to use the PCH PWM function. + The CPU PWM registers are all zero after reset. */ + if (conf->gpu_pch_backlight_pwm_hz) { + /* For Lynx Point-LP: + Reference clock is 24MHz. We can choose either a 16 + or a 128 step increment. Use 16 if we would have less + than 100 steps otherwise. */ + const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; + unsigned int pwm_increment, pwm_period; + u32 south_chicken2; + + south_chicken2 = gtt_read(SOUTH_CHICKEN2); + if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + pwm_increment = 16; + south_chicken2 &= ~(1 << 5); + } else { + pwm_increment = 128; + south_chicken2 |= 1 << 5; + } + gtt_write(SOUTH_CHICKEN2, south_chicken2); + + pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + /* Start with a 50% duty cycle. */ + gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); + + gtt_write(BLC_PWM_PCH_CTL1, + (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | + BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); } }
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35897 )
Change subject: [TEST] intel/broadwell: Implement proper backlight PWM config ......................................................................
Patch Set 1: Code-Review+1
verified working on google/lulu and purism/librem_13v1, but 183Hz backlight produced some odd graphical glitches on init. Using the linux i915 default of 200Hz resolved them.
PS - very much appreciate the level of detail in the commit msg
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35897 )
Change subject: [TEST] intel/broadwell: Implement proper backlight PWM config ......................................................................
Patch Set 1:
(1 comment)
Nice.
https://review.coreboot.org/c/coreboot/+/35897/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35897/1//COMMIT_MSG@27 PS1, Line 27: ! Keep?
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35897 )
Change subject: [TEST] intel/broadwell: Implement proper backlight PWM config ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35897/1/src/soc/intel/broadwell/igd... File src/soc/intel/broadwell/igd.c:
https://review.coreboot.org/c/coreboot/+/35897/1/src/soc/intel/broadwell/igd... PS1, Line 339: Remove?
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35897 )
Change subject: [TEST] intel/broadwell: Implement proper backlight PWM config ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35897/1/src/soc/intel/broadwell/igd... File src/soc/intel/broadwell/igd.c:
https://review.coreboot.org/c/coreboot/+/35897/1/src/soc/intel/broadwell/igd... PS1, Line 339:
Remove?
https://review.coreboot.org/c/coreboot/+/30246/1/src/soc/intel/skylake/graph...
:)
Hello Patrick Rudolph, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35897
to look at the new patch set (#2).
Change subject: intel/broadwell: Implement proper backlight PWM config ......................................................................
intel/broadwell: Implement proper backlight PWM config
Port the backlight-PWM handling from Skylake instead of the previously used Haswell version. We use a 200Hz PWM signal for all boards. Which is higher than the previous devicetree value, 183Hz, but that was over- ridden by the VBIOS anyway. 200Hz is still very low, considering LED backlights, but accurate values are unknown at this time.
Lynx Point, the PCH for Haswell and Broadwell, is a transition point for the backlight-PWM config. On platforms with a PCH, we have:
o Before Lynx Point: The CPU has no PWM pin and sends the PWM duty-cycle setting to the PCH. The PCH can choose to ignore that and use its own setting (BLM_PCH_OVERRIDE_ENABLE). We use the CPU setting on these platforms. o Lynx Point + Haswell: The CPU has an additional PWM pin but can be set up to send its setting to the PCH as before. The PCH can still choose to ignore that. We use the CPU setting with Haswell. o Lynx Point + Broadwell: The CPU can't send its setting to the PCH anymore. BLM_PCH_ OVERRIDE_ENABLE must always be set(!) if the PCH PWM pin is used (it virtually always is). We have to use the PCH setting in this case. o After Lynx Point: Same as with Broadwell, only BLM_PCH_OVERRIDE_ENABLE is implied and the bit not implemented anymore.
Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924 Signed-off-by: Nico Huber nico.h@gmx.de --- M src/mainboard/google/auron/variants/auron_paine/devicetree.cb M src/mainboard/google/auron/variants/auron_yuna/devicetree.cb M src/mainboard/google/auron/variants/buddy/devicetree.cb M src/mainboard/google/auron/variants/gandof/devicetree.cb M src/mainboard/google/auron/variants/lulu/devicetree.cb M src/mainboard/google/auron/variants/samus/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/igd.c 10 files changed, 49 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35897/2
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35897 )
Change subject: intel/broadwell: Implement proper backlight PWM config ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35897/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35897/1//COMMIT_MSG@27 PS1, Line 27: !
Keep?
Done
https://review.coreboot.org/c/coreboot/+/35897/1/src/soc/intel/broadwell/igd... File src/soc/intel/broadwell/igd.c:
https://review.coreboot.org/c/coreboot/+/35897/1/src/soc/intel/broadwell/igd... PS1, Line 339:
https://review.coreboot.org/c/coreboot/+/30246/1/src/soc/intel/skylake/graph... […]
Done?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35897 )
Change subject: intel/broadwell: Implement proper backlight PWM config ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35897 )
Change subject: intel/broadwell: Implement proper backlight PWM config ......................................................................
intel/broadwell: Implement proper backlight PWM config
Port the backlight-PWM handling from Skylake instead of the previously used Haswell version. We use a 200Hz PWM signal for all boards. Which is higher than the previous devicetree value, 183Hz, but that was over- ridden by the VBIOS anyway. 200Hz is still very low, considering LED backlights, but accurate values are unknown at this time.
Lynx Point, the PCH for Haswell and Broadwell, is a transition point for the backlight-PWM config. On platforms with a PCH, we have:
o Before Lynx Point: The CPU has no PWM pin and sends the PWM duty-cycle setting to the PCH. The PCH can choose to ignore that and use its own setting (BLM_PCH_OVERRIDE_ENABLE). We use the CPU setting on these platforms. o Lynx Point + Haswell: The CPU has an additional PWM pin but can be set up to send its setting to the PCH as before. The PCH can still choose to ignore that. We use the CPU setting with Haswell. o Lynx Point + Broadwell: The CPU can't send its setting to the PCH anymore. BLM_PCH_ OVERRIDE_ENABLE must always be set(!) if the PCH PWM pin is used (it virtually always is). We have to use the PCH setting in this case. o After Lynx Point: Same as with Broadwell, only BLM_PCH_OVERRIDE_ENABLE is implied and the bit not implemented anymore.
Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924 Signed-off-by: Nico Huber nico.h@gmx.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/35897 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/mainboard/google/auron/variants/auron_paine/devicetree.cb M src/mainboard/google/auron/variants/auron_yuna/devicetree.cb M src/mainboard/google/auron/variants/buddy/devicetree.cb M src/mainboard/google/auron/variants/gandof/devicetree.cb M src/mainboard/google/auron/variants/lulu/devicetree.cb M src/mainboard/google/auron/variants/samus/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/igd.c 10 files changed, 49 insertions(+), 34 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb index b31d829..f6ec15a 100644 --- a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb index 3c00ec9..db02565 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/buddy/devicetree.cb b/src/mainboard/google/auron/variants/buddy/devicetree.cb index f75da84..e12882f 100644 --- a/src/mainboard/google/auron/variants/buddy/devicetree.cb +++ b/src/mainboard/google/auron/variants/buddy/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb index 118e646..230f5bd 100644 --- a/src/mainboard/google/auron/variants/gandof/devicetree.cb +++ b/src/mainboard/google/auron/variants/gandof/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb index 622ea34..1983045 100644 --- a/src/mainboard/google/auron/variants/lulu/devicetree.cb +++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb @@ -9,9 +9,8 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb index a6c2fea..434ecc8 100644 --- a/src/mainboard/google/auron/variants/samus/devicetree.cb +++ b/src/mainboard/google/auron/variants/samus/devicetree.cb @@ -9,9 +9,8 @@ # Enable DDI2 Hotplug with 6ms pulse register "gpu_dp_c_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb index e713cd2..98b5163 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/devicetree.cb @@ -6,9 +6,8 @@ # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb index 3e83d3f..32c3ed1 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/devicetree.cb @@ -6,9 +6,8 @@ # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000200" + # Set backlight PWM value for eDP + register "gpu_pch_backlight_pwm_hz" = "200"
# Enable Panel and configure power delays register "gpu_panel_port_select" = "1" # eDP diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 456a435..18a6585 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -117,8 +117,11 @@ u16 gpu_panel_power_backlight_off_delay;
/* Panel backlight settings */ - u32 gpu_cpu_backlight; - u32 gpu_pch_backlight; + unsigned int gpu_pch_backlight_pwm_hz; + enum { + GPU_BACKLIGHT_POLARITY_HIGH = 0, + GPU_BACKLIGHT_POLARITY_LOW, + } gpu_pch_backlight_polarity;
/* * Graphics CD Clock Frequency diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index dab2d15..f4322bf 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -335,14 +335,34 @@ gtt_write(PCH_PP_DIVISOR, reg32); }
- /* Enable Backlight if needed */ - if (conf->gpu_cpu_backlight) { - gtt_write(BLC_PWM_CPU_CTL2, BLC_PWM2_ENABLE); - gtt_write(BLC_PWM_CPU_CTL, conf->gpu_cpu_backlight); - } - if (conf->gpu_pch_backlight) { - gtt_write(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE); - gtt_write(BLC_PWM_PCH_CTL2, conf->gpu_pch_backlight); + /* So far all devices seem to use the PCH PWM function. + The CPU PWM registers are all zero after reset. */ + if (conf->gpu_pch_backlight_pwm_hz) { + /* For Lynx Point-LP: + Reference clock is 24MHz. We can choose either a 16 + or a 128 step increment. Use 16 if we would have less + than 100 steps otherwise. */ + const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100; + unsigned int pwm_increment, pwm_period; + u32 south_chicken2; + + south_chicken2 = gtt_read(SOUTH_CHICKEN2); + if (conf->gpu_pch_backlight_pwm_hz > hz_limit) { + pwm_increment = 16; + south_chicken2 &= ~(1 << 5); + } else { + pwm_increment = 128; + south_chicken2 |= 1 << 5; + } + gtt_write(SOUTH_CHICKEN2, south_chicken2); + + pwm_period = 24 * 1000 * 1000 / pwm_increment / conf->gpu_pch_backlight_pwm_hz; + /* Start with a 50% duty cycle. */ + gtt_write(BLC_PWM_PCH_CTL2, pwm_period << 16 | pwm_period / 2); + + gtt_write(BLC_PWM_PCH_CTL1, + (conf->gpu_pch_backlight_polarity == GPU_BACKLIGHT_POLARITY_LOW) << 29 | + BLM_PCH_OVERRIDE_ENABLE | BLM_PCH_PWM_ENABLE); } }
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Arthur Heymans (Code Review) -
Matt DeVillier (Code Review)
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