Change in ...coreboot[master]: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode

[Frans Hendriks (Code Review)]

Hello Patrick Rudolph, Aaron Durbin, Piotr Król, Paul Menzel, build bot (Jenkins), Hannah Williams, Nico Huber, Michał Żygowski, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/29284

to look at the new patch set (#10).

Change subject: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
......................................................................

soc/intel/braswell/chip.c: Configure LPSS devices in correct mode

LPSS (SIO 0/24/0 and 0/30/0) are configured to ACPI mode if 'lpss_acpi_mode' = '1' or
PcdEnableDma0/PcdEnableDma1 is configured in ACPI mode. When function 0 is configured in
ACPI mode, functions > 1 are not available on the PCI bus, even pcdEnableXXXXX is set to
PCI mode.
For SIO DMA0:
 - HSUARTS ports not visible on PCI bus.
For SIO DMA1:
 - I2C ports not visible on PCI bus.

Force 'function > 1' devices in ACPI mode when function 0 is configured in ACPI
mode.

Intel FSP documentation does not mention that PcdEnable* devices in LPSS supports ACPI
Mode (value 0x2). For these devices value '0x1' is used for PCI Mode.

BUG=N/A
TEST=Intel Cherry Hill

Change-Id: Ie271d8cb9f30f0c0ba538f1530cfb82f1306fea8
Signed-off-by: Frans Hendriks 
---
M src/soc/intel/braswell/chip.c
1 file changed, 23 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29284/10