Change in coreboot[master]: soc/amd/common/block/cpu: Remove magic number in memlayout

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58377 )

Change subject: soc/amd/common/block/cpu: Remove magic number in memlayout
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soc/amd/common/block/cpu: Remove magic number in memlayout

The SPI DMA controller can only perform transactions on a cache line
boundary. This change removes the magic number and uses the #define to
make it clear.

BUG=b:179699789
TEST=Boot guybrush to OS

Signed-off-by: Raul E Rangel 
Change-Id: Ie7b851dc2433e44a23224c3ff733fdea5fbcca0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58377
Tested-by: build bot (Jenkins) 
Reviewed-by: Karthik Ramasubramanian 
---
M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Karthik Ramasubramanian: Looks good to me, approved

diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index 59631f3..005bde0 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -103,8 +103,8 @@
          * the payload on non-S3 boots, so we don't need to reserve it from the
          * OS. The 64 byte alignment is required by the SPI DMA controller.
          */
-        . = ALIGN(64);
-        REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, 64)
+        . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
+        REGION(payload_preload_cache, ., CONFIG_PAYLOAD_PRELOAD_CACHE_SIZE, ARCH_CACHELINE_ALIGN_SIZE)
 #endif

RAMSTAGE(CONFIG_RAMBASE, 8M)