Change in coreboot[master]: soc/intel/baytrail: Drop runtime ACPI mode change via SMI

[Matt DeVillier (Code Review)]

Attention is currently required from: Lance Zhao, Marc Jones, Martin Roth, Stefan Reinauer, Angel Pons, Kyösti Mälkki, Patrick Rudolph.
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49492 )

Change subject: soc/intel/baytrail: Drop runtime ACPI mode change via SMI
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Patch Set 6:

(1 comment)

Patchset:

PS1:
> Yes, I linked and read the commit this reverts, you are only answering what I was able to read there […]

best I can tell, the PCI-mode support for Baytrail LPSS devices is incomplete, since setting them to PCI mode in devicetree (as we've done with the ChromeOS Braswell boards) did not result in them being usable by the payload (either SeaBIOS or Tianocore). In my own tree, I've ended up doing an ugly hack where coreboot does the ACPI mode switch in the payload (as here, via SMM) so that the payload can detect/use the eMMC in PCI mode but the OS sees it in ACPI mode.

But as for the code removed in this patch, I'm not aware that it was ever actually used, even in shipped ChromeOS firmware. SeaBIOS on RAMBI-based boards required a special config to specify the MMIO base address of the eMMC/SD devices in ACPI mode, since depthcharge definitely did not switch them back to PCI mode.