Change in coreboot[master]: soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock - coreboot-gerrit

1 Nov 2019

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36550 )
Change subject: soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock
......................................................................
soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock
Clone entirely from Icelake
List of changes on top off initial icelake clone
1. Replace "Icelake" with "Tigerlake"
2. Replace "icl" with "tgl"
3. Replace "icp" with "tgp"
4. Rename structure based on Icelake with Tigerlake
5. Add CPU/PCH/SA EDS docuemnt number and chapter number
Tiger Lake specific changes will follow in subsequent patches.
1. Add Tigerlake specific device IDs (CPU/PCH/SA)
"The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware."
Change-Id: Id7a05f4b183028550d805f02a8078ab69862a62e
Signed-off-by: Subrata Banik subrata.banik@intel.com
---
A src/soc/intel/tigerlake/bootblock/bootblock.c
A src/soc/intel/tigerlake/bootblock/cpu.c
A src/soc/intel/tigerlake/bootblock/pch.c
A src/soc/intel/tigerlake/bootblock/report_platform.c
4 files changed, 479 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/36550/1

diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c
new file mode 100644
index 0000000..f6fe4c4
--- /dev/null
+++ b/src/soc/intel/tigerlake/bootblock/bootblock.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <intelblocks/gspi.h>
+#include <intelblocks/systemagent.h>
+#include <intelblocks/uart.h>
+#include <soc/bootblock.h>
+#include <soc/iomap.h>
+#include <soc/pch.h>
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+	/* Call lib/bootblock.c main */
+	bootblock_main_with_basetime(base_timestamp);
+}
+
+void bootblock_soc_early_init(void)
+{
+	bootblock_systemagent_early_init();
+	bootblock_pch_early_init();
+	bootblock_cpu_init();
+	pch_early_iorange_init();
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+		uart_bootblock_init();
+}
+
+void bootblock_soc_init(void)
+{
+	report_platform_info();
+	pch_early_init();
+}
diff --git a/src/soc/intel/tigerlake/bootblock/cpu.c b/src/soc/intel/tigerlake/bootblock/cpu.c
new file mode 100644
index 0000000..1bae4fa
--- /dev/null
+++ b/src/soc/intel/tigerlake/bootblock/cpu.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+  * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 6
+ */
+
+#include <intelblocks/fast_spi.h>
+#include <soc/bootblock.h>
+
+void bootblock_cpu_init(void)
+{
+	/*
+	 * Tigerlake platform doesn't support booting from any other media
+	 * (like eMMC on APL/GLK platform) than only booting from SPI device
+	 * and on IA platform SPI is memory mapped hence enabling temporarily
+	 * cacheing on memory-mapped spi boot media.
+	 *
+	 * This assumption will not hold good for APL/GLK platform where boot
+	 * from eMMC is also possible options.
+	 */
+	fast_spi_cache_bios_region();
+}
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
new file mode 100644
index 0000000..94b7f62
--- /dev/null
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor PCH Datasheet
+ * Document number: 575857
+ * Chapter number: 2, 3, 4, 27, 28
+ */
+
+#include <device/mmio.h>
+#include <device/device.h>
+#include <device/pci_ops.h>
+#include <intelblocks/fast_spi.h>
+#include <intelblocks/gspi.h>
+#include <intelblocks/lpc_lib.h>
+#include <intelblocks/p2sb.h>
+#include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/rtc.h>
+#include <intelblocks/smbus.h>
+#include <intelblocks/tco.h>
+#include <soc/bootblock.h>
+#include <soc/espi.h>
+#include <soc/iomap.h>
+#include <soc/p2sb.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <soc/pcr_ids.h>
+#include <soc/pm.h>
+#include <soc/smbus.h>
+
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x0600
+#define PCR_PSFX_TO_SHDW_BAR0	0
+#define PCR_PSFX_TO_SHDW_BAR1	0x4
+#define PCR_PSFX_TO_SHDW_BAR2	0x8
+#define PCR_PSFX_TO_SHDW_BAR3	0xC
+#define PCR_PSFX_TO_SHDW_BAR4	0x10
+#define PCR_PSFX_TO_SHDW_PCIEN_IOEN	0x01
+#define PCR_PSFX_T0_SHDW_PCIEN	0x1C
+
+#define PCR_DMI_DMICTL		0x2234
+#define  PCR_DMI_DMICTL_SRLOCK	(1 << 31)
+
+#define PCR_DMI_ACPIBA		0x27B4
+#define PCR_DMI_ACPIBDID	0x27B8
+#define PCR_DMI_PMBASEA		0x27AC
+#define PCR_DMI_PMBASEC		0x27B0
+
+#define PCR_DMI_LPCIOD		0x2770
+#define PCR_DMI_LPCIOE		0x2774
+
+static void soc_config_pwrmbase(void)
+{
+	uint32_t reg32;
+
+	/*
+	 * Assign Resources to PWRMBASE
+	 * Clear BIT 1-2  Command Register
+	 */
+	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
+	reg32 &= ~(PCI_COMMAND_MEMORY);
+	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+
+	/* Program PWRM Base */
+	pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS);
+
+	/* Enable Bus Master and MMIO Space */
+	reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MEMORY;
+	pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
+
+	/* Enable PWRM in PMC */
+	reg32 = read32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL));
+	write32((void *)(PCH_PWRM_BASE_ADDRESS + ACTL), reg32 | PWRM_EN);
+}
+
+void bootblock_pch_early_init(void)
+{
+	fast_spi_early_init(SPI_BASE_ADDRESS);
+	gspi_early_bar_init();
+	p2sb_enable_bar();
+	p2sb_configure_hpet();
+
+	/*
+	 * Enabling PWRM Base for accessing
+	 * Global Reset Cause Register.
+	 */
+	soc_config_pwrmbase();
+}
+
+
+static void soc_config_acpibase(void)
+{
+	uint32_t pmc_reg_value;
+
+	pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
+						PCR_PSFX_TO_SHDW_BAR4);
+
+	if (pmc_reg_value != 0xFFFFFFFF) {
+		/* Disable Io Space before changing the address */
+		pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
+				PCR_PSFX_T0_SHDW_PCIEN,
+				~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
+		/* Program ABASE in PSF3 PMC space BAR4*/
+		pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
+				PCR_PSFX_TO_SHDW_BAR4,
+				ACPI_BASE_ADDRESS);
+		/* Enable IO Space */
+		pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
+				PCR_PSFX_T0_SHDW_PCIEN,
+				~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
+	}
+}
+
+static int pch_check_decode_enable(void)
+{
+	uint32_t dmi_control;
+
+	/*
+	 * This cycle decoding is only allowed to set when
+	 * DMICTL.SRLOCK is 0.
+	 */
+	dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
+	if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
+		return -1;
+	return 0;
+}
+
+void pch_early_iorange_init(void)
+{
+	uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+		LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
+
+	/* IO Decode Range */
+	if (CONFIG(DRIVERS_UART_8250IO))
+		lpc_io_setup_comm_a_b();
+
+	/* IO Decode Enable */
+	if (pch_check_decode_enable() == 0) {
+		io_enables = lpc_enable_fixed_io_ranges(io_enables);
+		/*
+		 * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
+		 * value program in ESPI PCI offset 82h.
+		 */
+		pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+	}
+
+	/* Program generic IO Decode Range */
+	pch_enable_lpc();
+}
+
+void pch_early_init(void)
+{
+	/*
+	 * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
+	 * GPE0_STS, GPE0_EN registers.
+	 */
+	soc_config_acpibase();
+
+	/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
+	tco_configure();
+
+	/* Program SMBUS_BASE_ADDRESS and Enable it */
+	smbus_common_init();
+
+	/* Set up GPE configuration */
+	pmc_gpe_init();
+
+	enable_rtc_upper_bank();
+}
diff --git a/src/soc/intel/tigerlake/bootblock/report_platform.c b/src/soc/intel/tigerlake/bootblock/report_platform.c
new file mode 100644
index 0000000..a5b39c0
--- /dev/null
+++ b/src/soc/intel/tigerlake/bootblock/report_platform.c
@@ -0,0 +1,216 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This file is created based on Intel Tiger Lake Processor ID datasheet
+ * Document number: 576591
+ * Chapter number: 2
+ */
+
+#include <arch/cpu.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <intelblocks/mp_init.h>
+#include <soc/bootblock.h>
+#include <soc/pch.h>
+#include <soc/pci_devs.h>
+#include <string.h>
+
+#define BIOS_SIGN_ID	0x8B
+
+static struct {
+	u32 cpuid;
+	const char *name;
+} cpu_table[] = {
+	{ CPUID_ICELAKE_A0, "Icelake A0" },
+	{ CPUID_ICELAKE_B0, "Icelake B0" },
+};
+
+static struct {
+	u16 mchid;
+	const char *name;
+} mch_table[] = {
+	{ PCI_DEVICE_ID_INTEL_ICL_ID_U, "Icelake-U" },
+	{ PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, "Icelake-U-2-2" },
+	{ PCI_DEVICE_ID_INTEL_ICL_ID_Y, "Icelake-Y" },
+	{ PCI_DEVICE_ID_INTEL_ICL_ID_Y_2, "Icelake-Y-2" },
+};
+
+static struct {
+	u16 espiid;
+	const char *name;
+} pch_table[] = {
+	{ PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, "Icelake-U Base" },
+	{ PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, "Icelake-Y Base" },
+	{ PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, "Icelake-U Premium" },
+	{ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, "Icelake-U Super" },
+	{ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, "Icelake-U Super REV0" },
+	{ PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, "Icelake-Y Super" },
+	{ PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, "Icelake-Y Premium" },
+};
+
+static struct {
+	u16 igdid;
+	const char *name;
+} igd_table[] = {
+	{ PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, "Icelake ULT GT0" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, "Icelake ULT GT0.5" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, "Icelake U GT1" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_0, "Icelake Y GT2" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_1, "Icelake Y GT2_1" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_1, "Icelake U GT2_1" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_2, "Icelake Y GT2_2" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_2, "Icelake U GT2_2" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_3, "Icelake Y GT2_3" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_3, "Icelake U GT2_3" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_4, "Icelake Y GT2_4" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_4, "Icelake U GT2_4" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULX_5, "Icelake Y GT2_5" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT2_ULT_5, "Icelake U GT2_5" },
+	{ PCI_DEVICE_ID_INTEL_ICL_GT3_ULT, "Icelake U GT3" },
+};
+
+static uint8_t get_dev_revision(pci_devfn_t dev)
+{
+	return pci_read_config8(dev, PCI_REVISION_ID);
+}
+
+static uint16_t get_dev_id(pci_devfn_t dev)
+{
+	return pci_read_config16(dev, PCI_DEVICE_ID);
+}
+
+static void report_cpu_info(void)
+{
+	struct cpuid_result cpuidr;
+	u32 i, index, cpu_id, cpu_feature_flag;
+	const char cpu_not_found[] = "Platform info not available";
+	const char *cpu_name = cpu_not_found; /* 48 bytes are reported */
+	int vt, txt, aes;
+	msr_t microcode_ver;
+	static const char *const mode[] = {"NOT ", ""};
+	const char *cpu_type = "Unknown";
+	u32 p[13];
+
+	index = 0x80000000;
+	cpuidr = cpuid(index);
+	if (cpuidr.eax >= 0x80000004) {
+		int j = 0;
+
+		for (i = 2; i <= 4; i++) {
+			cpuidr = cpuid(index + i);
+			p[j++] = cpuidr.eax;
+			p[j++] = cpuidr.ebx;
+			p[j++] = cpuidr.ecx;
+			p[j++] = cpuidr.edx;
+		}
+		p[12] = 0;
+		cpu_name = (char *)p;
+
+		/* Skip leading spaces in CPU name string */
+		while (cpu_name[0] == ' ' && strlen(cpu_name) > 0)
+			cpu_name++;
+	}
+
+	microcode_ver.lo = 0;
+	microcode_ver.hi = 0;
+	wrmsr(BIOS_SIGN_ID, microcode_ver);
+	cpu_id = cpu_get_cpuid();
+	microcode_ver = rdmsr(BIOS_SIGN_ID);
+
+	/* Look for string to match the name */
+	for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
+		if (cpu_table[i].cpuid == cpu_id) {
+			cpu_type = cpu_table[i].name;
+			break;
+		}
+	}
+
+	printk(BIOS_DEBUG, "CPU: %s\n", cpu_name);
+	printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n",
+	       cpu_id, cpu_type, microcode_ver.hi);
+
+	cpu_feature_flag = cpu_get_feature_flags_ecx();
+	aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
+	txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
+	vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
+	printk(BIOS_DEBUG,
+		"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
+		mode[aes], mode[txt], mode[vt]);
+}
+
+static void report_mch_info(void)
+{
+	int i;
+	pci_devfn_t dev = SA_DEV_ROOT;
+	uint16_t mchid = get_dev_id(dev);
+	uint8_t mch_revision = get_dev_revision(dev);
+	const char *mch_type = "Unknown";
+
+	for (i = 0; i < ARRAY_SIZE(mch_table); i++) {
+		if (mch_table[i].mchid == mchid) {
+			mch_type = mch_table[i].name;
+			break;
+		}
+	}
+
+	printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n",
+		mchid, mch_revision, mch_type);
+}
+
+static void report_pch_info(void)
+{
+	int i;
+	pci_devfn_t dev = PCH_DEV_ESPI;
+	uint16_t espiid = get_dev_id(dev);
+	const char *pch_type = "Unknown";
+
+	for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
+		if (pch_table[i].espiid == espiid) {
+			pch_type = pch_table[i].name;
+			break;
+		}
+	}
+	printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
+		espiid, get_dev_revision(dev), pch_type);
+}
+
+static void report_igd_info(void)
+{
+	int i;
+	pci_devfn_t dev = SA_DEV_IGD;
+	uint16_t igdid = get_dev_id(dev);
+	const char *igd_type = "Unknown";
+
+	for (i = 0; i < ARRAY_SIZE(igd_table); i++) {
+		if (igd_table[i].igdid == igdid) {
+			igd_type = igd_table[i].name;
+			break;
+		}
+	}
+	printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n",
+		igdid, get_dev_revision(dev), igd_type);
+}
+
+void report_platform_info(void)
+{
+	report_cpu_info();
+	report_mch_info();
+	report_pch_info();
+	report_igd_info();
+}
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id7a05f4b183028550d805f02a8078ab69862a62e
Gerrit-Change-Number: 36550
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik subrata.banik@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Subrata Banik subrata.banik@intel.com
Gerrit-MessageType: newchange



    