Change in coreboot[master]: soc/intel/alderlake: Disable VT-d for early silicons

[Meera Ravindranath (Code Review)]

Attention is currently required from:  Felix Singer, Abhijeet Rao, Maulik V Vaghela, Tim Wawrzynczak, Patrick Rudolph.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59191 )

Change subject: soc/intel/alderlake: Disable VT-d for early silicons
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Patch Set 6:

(1 comment)

File src/soc/intel/alderlake/romstage/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/59191/comment/a900de37_582128d6 
PS5, Line 263: 	const uint32_t cpuid = cpu_get_cpuid();
> I would add a comment here that Vt-D is broken on these models and that it results in a CPU hang if  […]

Done