New patch to review for coreboot: 956fed3 intel/bd82x6x: Add Kconfig options for USB debug port

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3240

-gerrit

commit 956fed3e2d85999390a7c02460c1afd1095668ca
Author: Vladimir Serbinenko 
Date:   Sun Mar 31 22:22:10 2013 +0200

intel/bd82x6x: Add Kconfig options for USB debug port

Nowadays, chipsets or boards do not only have one USB port with
    the capabilities of a debug port but several ones. Some of these
    ports are easier accessible than others, so making them configurable
    is quite useful.

This applies also to the Intel BD82x6x chipset.

For example on the Lenovo X201 with a Mobile Intel QM57 Express
    Chipset [1][2], the yellow, always powered port on the left under the
    PCMCIA card slot is D26:F0 is easier accesible than device D29:F7.

[1] http://thinkwiki.de/X201
    [2] http://en.wikipedia.org/wiki/Intel_5_Series

Change-Id: I7447114a03eb0e98caaaf42ddfe3c678601e6c66
    Signed-off-by: Vladimir Serbinenko 
    Signed-off-by: Paul Menzel 
---
 src/southbridge/intel/bd82x6x/Kconfig     |  8 ++++++++
 src/southbridge/intel/bd82x6x/usb_debug.c |  2 +-
 src/southbridge/intel/bd82x6x/usb_ehci.c  | 28 +++++++++++++++++-----------
 3 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 5dd492c..56471bc 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -72,4 +72,12 @@ config LOCK_MANAGEMENT_ENGINE

If unsure, say N.

+config USBDEBUG_DEV
+	int
+	default 29
+
+config USBDEBUG_FUNC
+	int
+	default 7
+
 endif
diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c
index 79a43bd..706b97c 100644
--- a/src/southbridge/intel/bd82x6x/usb_debug.c
+++ b/src/southbridge/intel/bd82x6x/usb_debug.c
@@ -28,7 +28,7 @@
 void enable_usbdebug(unsigned int port)
 {
    u32 dbgctl;
-	device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
+	device_t dev = PCI_DEV(0, CONFIG_USBDEBUG_DEV, CONFIG_USBDEBUG_FUNC);

/* Set the EHCI BAR address. */
    pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index aec230c..3b8b082 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -68,22 +68,28 @@ static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned devic
 static void usb_ehci_set_resources(struct device *dev)
 {
 #if CONFIG_USBDEBUG
-	struct resource *res;
-	u32 base;
-	u32 usb_debug;
+	u32 usb_debug = 0;

-	usb_debug = get_ehci_debug();
-	set_ehci_debug(0);
+	if (dev->path.pci.devfn == PCI_DEVFN (CONFIG_USBDEBUG_DEV, CONFIG_USBDEBUG_FUNC))
+	{
+		usb_debug = get_ehci_debug();
+		set_ehci_debug(0);
+	}
 #endif
    pci_dev_set_resources(dev);

#if CONFIG_USBDEBUG
-	res = find_resource(dev, 0x10);
-	set_ehci_debug(usb_debug);
-	if (!res) return;
-	base = res->base;
-	set_ehci_base(base);
-	report_resource_stored(dev, res, "");
+	if (dev->path.pci.devfn == PCI_DEVFN (CONFIG_USBDEBUG_DEV, CONFIG_USBDEBUG_FUNC))
+	{
+		struct resource *res;
+		u32 base;
+		res = find_resource(dev, 0x10);
+		if (!res) return;
+		base = res->base;
+		set_ehci_debug(usb_debug);
+		set_ehci_base(base);
+		report_resource_stored(dev, res, "");
+	}
 #endif
 }