Change in coreboot[master]: soc/intel/tigerlake: Refactor TCSS ASL to add \_SB.PCI1 support
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41024 )
Change subject: soc/intel/tigerlake: Refactor TCSS ASL to add _SB.PCI1 support ......................................................................
soc/intel/tigerlake: Refactor TCSS ASL to add _SB.PCI1 support
Refer to https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon...
Include TCSS TBT PCIE Root Port 0/1/2/3 inside _SB.PCIx (where x depends on PCI multiple segment support).
Change-Id: Ia2935af79d8589a60f3c4e5a0b585f5b6dd19a32 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/intel/tglrvp/dsdt.asl M src/soc/intel/tigerlake/acpi/tcss.asl 3 files changed, 29 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/41024/1
diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl index a87c743..5997ccc 100644 --- a/src/mainboard/google/volteer/dsdt.asl +++ b/src/mainboard/google/volteer/dsdt.asl @@ -31,8 +31,8 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> - #include <soc/intel/tigerlake/acpi/tcss.asl> } + #include <soc/intel/tigerlake/acpi/tcss.asl> /* Mainboard hooks */ #include "mainboard.asl" } diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl index c66e972..2576596 100644 --- a/src/mainboard/intel/tglrvp/dsdt.asl +++ b/src/mainboard/intel/tglrvp/dsdt.asl @@ -27,8 +27,8 @@ { #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/tigerlake/acpi/southbridge.asl> - #include <soc/intel/tigerlake/acpi/tcss.asl> } + #include <soc/intel/tigerlake/acpi/tcss.asl> }
#if CONFIG(CHROMEOS) diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 9f03aa9..86536bc 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -19,6 +19,10 @@ #define TCSS_XDCI 5 #define TCSS_DMA0 6 #define TCSS_DMA1 7 +#define TCSS_TBT_PCIE1_RP0 8 +#define TCSS_TBT_PCIE1_RP1 9 +#define TCSS_TBT_PCIE1_RP2 10 +#define TCSS_TBT_PCIE1_RP3 11
/* * MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE @@ -681,7 +685,13 @@ } #include "tcss_dma.asl" } - +} +#if CONFIG_PCI_SEGMENT_GROUPS > 1 +Scope (_SB.PCI1) +#else +Scope (_SB.PCI0) +#endif +{ /* * TCSS PCIE Root Port #00 */ @@ -692,8 +702,11 @@ Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ Name (LMSL, 0) /* PCIE LTR max snoop Latency */ Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + Name (DCPM, TCSS_TBT_PCIE1_RP0) +#else Name (DCPM, TCSS_TBT_PCIE0_RP0) - +#endif Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -717,8 +730,11 @@ Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ Name (LMSL, 0) /* PCIE LTR max snoop Latency */ Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + Name (DCPM, TCSS_TBT_PCIE1_RP1) +#else Name (DCPM, TCSS_TBT_PCIE0_RP1) - +#endif Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -742,8 +758,11 @@ Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ Name (LMSL, 0) /* PCIE LTR max snoop Latency */ Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + Name (DCPM, TCSS_TBT_PCIE1_RP2) +#else Name (DCPM, TCSS_TBT_PCIE0_RP2) - +#endif Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -767,8 +786,11 @@ Name (LTEN, 0) /* Latency Tolerance Reporting Mechanism, 0:Disable, 1:Enable */ Name (LMSL, 0) /* PCIE LTR max snoop Latency */ Name (LNSL, 0) /* PCIE LTR max no snoop Latency */ +#if CONFIG_PCI_SEGMENT_GROUPS > 1 + Name (DCPM, TCSS_TBT_PCIE1_RP3) +#else Name (DCPM, TCSS_TBT_PCIE0_RP3) - +#endif Method (_STA, 0x0, NotSerialized) { Return (0x0F)
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41024
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Refactor TCSS ASL to add _SB.PCI1 support ......................................................................
soc/intel/tigerlake: Refactor TCSS ASL to add _SB.PCI1 support
Refer to https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon...
Include TCSS TBT PCIE Root Port 0/1/2/3 inside _SB.PCIx (where x depends on PCI multiple segment support).
Change-Id: Ia2935af79d8589a60f3c4e5a0b585f5b6dd19a32 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/intel/tglrvp/dsdt.asl M src/soc/intel/tigerlake/acpi/tcss.asl 3 files changed, 126 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/41024/2
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41024
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Refactor TCSS ASL to add _SB.PCI1 support ......................................................................
soc/intel/tigerlake: Refactor TCSS ASL to add _SB.PCI1 support
Refer to https://github.com/otcshare/CCG-TGL-Generic-SiC/blob/master/ClientOneSilicon...
Include TCSS TBT PCIE Root Port 0/1/2/3 inside _SB.PCIx (where x depends on PCI multiple segment support).
Change-Id: Ia2935af79d8589a60f3c4e5a0b585f5b6dd19a32 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/mainboard/google/volteer/dsdt.asl M src/mainboard/intel/tglrvp/dsdt.asl M src/soc/intel/tigerlake/acpi/tcss.asl 3 files changed, 85 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/41024/3
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41024 )
Change subject: soc/intel/tigerlake: Refactor TCSS ASL to add _SB.PCI1 support ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41024/3/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/tcss.asl:
https://review.coreboot.org/c/coreboot/+/41024/3/src/soc/intel/tigerlake/acp... PS3, Line 507: PCI1 So we're just repeating the same code but changing the path? Also, if segment groups are > 1 why are we assuming the device is living on segment 1. What if it's segment 2?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41024 )
Change subject: soc/intel/tigerlake: Refactor TCSS ASL to add _SB.PCI1 support ......................................................................
Patch Set 3:
Hi Subrata, please remember change deltaur which used TGL too. So I don't need to find which CL I need to follow 😊
Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41024?usp=email )
Change subject: soc/intel/tigerlake: Refactor TCSS ASL to add _SB.PCI1 support ......................................................................
Abandoned
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Aaron Durbin (Code Review) -
EricR Lai (Code Review)
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Stefan Reinauer (Code Review)
-
Subrata Banik (Code Review)