Change in coreboot[master]: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17

[Johnny Lin (Code Review)]

Hello build bot (Jenkins), Marc Jones, Patrick Georgi, Martin Roth, John Looney, Patrick Rudolph, Jonathan Zhang, Jingle Hsu, Angel Pons, Morgan Jang, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45798

to look at the new patch set (#7).

Change subject: soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17
......................................................................

soc/intel/xeon_sp/cpx: Add save_dimm_info for SMBIOS type 17

For now only implement for one socket and some of the fields
are hard-coded for DDR4 including memory device type, data width,
voltage and ECC support.

Change-Id: I3cb72d18027d972140828970206834ff55b72022
Signed-off-by: Johnny Lin 
---
M src/soc/intel/xeon_sp/cpx/Makefile.inc
A src/soc/intel/xeon_sp/cpx/ddr.c
A src/soc/intel/xeon_sp/cpx/include/soc/ddr.h
M src/soc/intel/xeon_sp/cpx/romstage.c
M src/soc/intel/xeon_sp/include/soc/romstage.h
M src/soc/intel/xeon_sp/romstage.c
6 files changed, 216 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/45798/7