Change in coreboot[master]: soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver

[Marshall Dawson (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Felix Held.
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52584 )

Change subject: soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver
......................................................................

Patch Set 4:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/52584/comment/70e464a5_2ab6988e 
PS4, Line 19: access it.
I think Felix was simply saying that he's _still_ able to access the region after the changes.  The approach didn't change much, i.e. the region is still above cbmem.
> What changed? Was the initial diagnosis wrong?

However, this is an interesting topic.  CB:49799 is fairly modern and seems to put Intel's BERT table into cbmem.  I don't understand how that should work; haven't looked to see whether the driver's been updated.