Patch set updated for coreboot: 6ad7eda CBMEM: Add cbmem_late_set_table() and drop references to high_tables_base

[Kyösti Mälkki]

Kyösti Mälkki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3902

-gerrit

commit 6ad7edab77122592b757d27aff23868c82925140
Author: Kyösti Mälkki 
Date:   Wed Sep 4 13:05:01 2013 +0300

CBMEM: Add cbmem_late_set_table() and drop references to high_tables_base

This helper function is for compatibility only for chipsets that do
    not implement get_top_of_ram() to support early CBMEM.

Also remove references to globals high_tables_base and _size under
    arch/ and from two ARMv7 boards.

Change-Id: I17eee30635a0368b2ada06e0698425c5ef0ecc53
    Signed-off-by: Kyösti Mälkki 
---
 src/arch/armv7/tables.c               |  7 -------
 src/arch/x86/boot/cbmem.c             |  5 +----
 src/arch/x86/boot/tables.c            |  2 --
 src/include/cbmem.h                   |  1 +
 src/lib/cbmem.c                       | 10 ++++++++++
 src/mainboard/google/pit/mainboard.c  | 17 +++++++++++------
 src/mainboard/google/snow/mainboard.c | 17 +++++++++++------
 7 files changed, 34 insertions(+), 25 deletions(-)

diff --git a/src/arch/armv7/tables.c b/src/arch/armv7/tables.c
index 0fc7399..0f174d3 100644
--- a/src/arch/armv7/tables.c
+++ b/src/arch/armv7/tables.c
@@ -29,13 +29,6 @@

#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)

-/*
- * TODO: "High" tables are a convention used on x86. Maybe we can
- * clean up that naming at some point.
- */
-uint64_t high_tables_base = 0;
-uint64_t high_tables_size;
-
 void cbmem_arch_init(void)
 {
 }
diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c
index 3f738be..6ec005d 100644
--- a/src/arch/x86/boot/cbmem.c
+++ b/src/arch/x86/boot/cbmem.c
@@ -25,9 +25,6 @@
  */
 void set_top_of_ram(uint64_t ramtop)
 {
-	high_tables_base = ramtop - HIGH_MEMORY_SIZE;
-	high_tables_size = HIGH_MEMORY_SIZE;
-	printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n",
-		high_tables_base, high_tables_size);
+	cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE);
 }
 #endif
diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c
index 67d7911..81d5453 100644
--- a/src/arch/x86/boot/tables.c
+++ b/src/arch/x86/boot/tables.c
@@ -32,8 +32,6 @@
 #include <lib.h>
 #include <smbios.h>

-uint64_t high_tables_base = 0;
-uint64_t high_tables_size;

void cbmem_arch_init(void)
 {
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 00d74d6..3d04763 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -137,6 +137,7 @@ void cbmem_add_lb_mem(struct lb_memory *mem);
 #ifndef __PRE_RAM__
 extern uint64_t high_tables_base, high_tables_size;
 void set_top_of_ram(uint64_t ramtop);
+void cbmem_late_set_table(uint64_t base, uint64_t size);
 void set_cbmem_toc(struct cbmem_entry *);
 #endif

diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 9e2ce0d..206fdbf 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -42,6 +42,8 @@ struct cbmem_entry {
 } __attribute__((packed));

#ifndef __PRE_RAM__
+uint64_t high_tables_base = 0;
+uint64_t high_tables_size = 0;
 static struct cbmem_entry *bss_cbmem_toc;

struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
@@ -60,7 +62,15 @@ struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void)
    printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_toc() for your chipset\n");
    return NULL;
 }
+#endif

+#if !defined(__PRE_RAM__)
+void cbmem_late_set_table(uint64_t base, uint64_t size)
+{
+	printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", base, base+size-1, __FUNCTION__);
+	high_tables_base = base;
+	high_tables_size = size;
+}
 #endif

/**
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 54ea042..7dd8388 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -221,17 +221,22 @@ static void mainboard_init(device_t dev)
    // gpio_info();
 }

+static void setup_cbmem(void)
+{
+	u64 size = CONFIG_COREBOOT_TABLES_SIZE;
+	u64 base = CONFIG_SYS_SDRAM_BASE +
+				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
+				CONFIG_COREBOOT_TABLES_SIZE;
+	cbmem_late_set_table(base, size);
+	cbmem_init(base, size);
+}
+
 static void mainboard_enable(device_t dev)
 {
    dev->ops->init = &mainboard_init;

/* set up coreboot tables */
-	/* FIXME: this should happen somewhere else */
-	high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
-	high_tables_base = CONFIG_SYS_SDRAM_BASE +
-				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
-				CONFIG_COREBOOT_TABLES_SIZE;
-	cbmem_init(high_tables_base, high_tables_size);
+	setup_cbmem();

/* set up dcache and MMU */
    /* FIXME: this should happen via resource allocator */
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index 5aedac9..8805be5 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -262,17 +262,22 @@ static void mainboard_init(device_t dev)
    // gpio_info();
 }

+static void setup_cbmem(void)
+{
+	u64 size = CONFIG_COREBOOT_TABLES_SIZE;
+	u64 base = CONFIG_SYS_SDRAM_BASE +
+				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
+				CONFIG_COREBOOT_TABLES_SIZE;
+	cbmem_late_set_table(base, size);
+	cbmem_init(base, size);
+}
+
 static void mainboard_enable(device_t dev)
 {
    dev->ops->init = &mainboard_init;

/* set up coreboot tables */
-	/* FIXME: this should happen somewhere else */
-	high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
-	high_tables_base = CONFIG_SYS_SDRAM_BASE +
-				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -
-				CONFIG_COREBOOT_TABLES_SIZE;
-	cbmem_init(high_tables_base, high_tables_size);
+	setup_cbmem();

/* set up dcache and MMU */
    /* FIXME: this should happen via resource allocator */