Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81570?usp=email )
Change subject: soc/intel/xeon_sp: Add soc_add_stack_mmios ......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1: SPR MTRR before:
[0m[DEBUG] MTRR: Physical address space:[0m [0m[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6[0m [0m[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0[0m [0m[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6[0m [0m[DEBUG] 0x0000000080000000 - 0x00000000ffffffff size 0x80000000 type 0[0m [0m[DEBUG] 0x0000000100000000 - 0x000000207fffffff size 0x1f80000000 type 6[0m [0m[DEBUG] 0x0000200000000000 - 0x00002064ffffffff size 0x6500000000 type 0[0m [0m[DEBUG] 0x0000206a00000000 - 0x00002074ffffffff size 0xb00000000 type 0[0m [0m[DEBUG] 0x0000207a00000000 - 0x00002084ffffffff size 0xb00000000 type 0[0m [0m[DEBUG] 0x0000208a00000000 - 0x00002094ffffffff size 0xb00000000 type 0[0m [0m[DEBUG] 0x0000209a00000000 - 0x00002104ffffffff size 0x6b00000000 type 0[0m [0m[DEBUG] 0x0000210a00000000 - 0x00002114ffffffff size 0xb00000000 type 0[0m [0m[DEBUG] 0x0000211a00000000 - 0x00002124ffffffff size 0xb00000000 type 0[0m [0m[DEBUG] 0x0000212a00000000 - 0x00002134ffffffff size 0xb00000000 type 0[0m [0m[DEBUG] 0x0000213a00000000 - 0x0000213fffffffff size 0x600000000 type 0[0m
[0m[DEBUG] MTRR: default type WB/UC MTRR counts: 37/7.[0m [0m[DEBUG] MTRR: UC selected as default type.[0m [0m[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x000fffff80000000 type 6[0m [0m[DEBUG] MTRR: 1 base 0x0000000100000000 mask 0x000fffff00000000 type 6[0m [0m[DEBUG] MTRR: 2 base 0x0000000200000000 mask 0x000ffffe00000000 type 6[0m [0m[DEBUG] MTRR: 3 base 0x0000000400000000 mask 0x000ffffc00000000 type 6[0m [0m[DEBUG] MTRR: 4 base 0x0000000800000000 mask 0x000ffff800000000 type 6[0m [0m[DEBUG] MTRR: 5 base 0x0000001000000000 mask 0x000ffff000000000 type 6[0m [0m[DEBUG] MTRR: 6 base 0x0000002000000000 mask 0x000fffff80000000 type 6[0m
SPR MTRR after:
[0m[DEBUG] MTRR: Physical address space:[0m [0m[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6[0m [0m[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0[0m [0m[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6[0m [0m[DEBUG] 0x0000000080000000 - 0x00000000ffffffff size 0x80000000 type 0[0m [0m[DEBUG] 0x0000000100000000 - 0x000000207fffffff size 0x1f80000000 type 6[0m [0m[DEBUG] 0x0000200000000000 - 0x0000213fffffffff size 0x14000000000 type 0[0m
[0m[DEBUG] MTRR: default type WB/UC MTRR counts: 3/7.[0m [0m[DEBUG] MTRR: WB selected as default type.[0m [0m[DEBUG] MTRR: 0 base 0x0000000080000000 mask 0x000fffff80000000 type 0[0m [0m[DEBUG] MTRR: 1 base 0x0000200000000000 mask 0x000fff0000000000 type 0[0m [0m[DEBUG] MTRR: 2 base 0x0000210000000000 mask 0x000fffc000000000 type 0[0m
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Shuo Liu (Code Review)