[XS] Change in coreboot[main]: soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82081?usp=email )

(

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP
......................................................................

soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP

In a server platform many silicon specific register lock operations
are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option
to make sure the codes could be used out-of-box to build products.

Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b
Signed-off-by: Shuo Liu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/lockdown.c
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  Patrick Rudolph: Looks good to me, approved
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c
index 9e25920..a3d17b4 100644
--- a/src/soc/intel/xeon_sp/lockdown.c
+++ b/src/soc/intel/xeon_sp/lockdown.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <intelblocks/cfg.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelpch/lockdown.h>
 #include <soc/lockdown.h>
@@ -20,6 +21,9 @@

void soc_lockdown_config(int chipset_lockdown)
 {
+	if (chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
+		return;
+
    lpc_lockdown_config();
    pmc_lockdown_config();
    sata_lockdown_config(chipset_lockdown);