New subject: Change in coreboot[master]: mb/hp/280_g2: Add new mainboard

6 Dec 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48386 )
Change subject: [WIP] mb/hp/280_g2: Add new mainboard
......................................................................
[WIP] mb/hp/280_g2: Add new mainboard
Boots fine and most things work, but still needs some work. S3 resume is
not working for some reason, though...
Change-Id: Iadf11c187307a24b15039a5a716737d9d74944e6
Signed-off-by: Angel Pons th3fanbus@gmail.com
---
A src/mainboard/hp/280_g2/Kconfig
A src/mainboard/hp/280_g2/Kconfig.name
A src/mainboard/hp/280_g2/Makefile.inc
A src/mainboard/hp/280_g2/acpi/ec.asl
A src/mainboard/hp/280_g2/acpi/superio.asl
A src/mainboard/hp/280_g2/board_info.txt
A src/mainboard/hp/280_g2/devicetree.cb
A src/mainboard/hp/280_g2/dsdt.asl
A src/mainboard/hp/280_g2/gma-mainboard.ads
A src/mainboard/hp/280_g2/gpio.c
A src/mainboard/hp/280_g2/gpio.h
A src/mainboard/hp/280_g2/ramstage.c
A src/mainboard/hp/280_g2/romstage.c
13 files changed, 551 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/48386/1

diff --git a/src/mainboard/hp/280_g2/Kconfig b/src/mainboard/hp/280_g2/Kconfig
new file mode 100644
index 0000000..6696fc6
--- /dev/null
+++ b/src/mainboard/hp/280_g2/Kconfig
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_HP_280_G2
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MAINBOARD_HAS_LIBGFXINIT
+	select SOC_INTEL_KABYLAKE
+	select SPD_READ_BY_WORD
+	select SKYLAKE_SOC_PCH_H
+
+config MAINBOARD_DIR
+	string
+	default "hp/280_g2"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "280 G2"
+
+config MAX_CPUS
+	int
+	default 8
+
+config DIMM_MAX
+	int
+	default 2
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+config UART_PCI_ADDR
+	default 0x00190000
+
+config USE_LEGACY_8254_TIMER
+	default y
+
+endif
diff --git a/src/mainboard/hp/280_g2/Kconfig.name b/src/mainboard/hp/280_g2/Kconfig.name
new file mode 100644
index 0000000..74ddaf4
--- /dev/null
+++ b/src/mainboard/hp/280_g2/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_HP_280_G2
+	bool "280 G2"
diff --git a/src/mainboard/hp/280_g2/Makefile.inc b/src/mainboard/hp/280_g2/Makefile.inc
new file mode 100644
index 0000000..9cb1c93
--- /dev/null
+++ b/src/mainboard/hp/280_g2/Makefile.inc
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += gpio.c
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/hp/280_g2/acpi/ec.asl b/src/mainboard/hp/280_g2/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/hp/280_g2/acpi/ec.asl
diff --git a/src/mainboard/hp/280_g2/acpi/superio.asl b/src/mainboard/hp/280_g2/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/hp/280_g2/acpi/superio.asl
diff --git a/src/mainboard/hp/280_g2/board_info.txt b/src/mainboard/hp/280_g2/board_info.txt
new file mode 100644
index 0000000..2495346
--- /dev/null
+++ b/src/mainboard/hp/280_g2/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: HP
+Board name: 280 G2
+Category: desktop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb
new file mode 100644
index 0000000..77b5028
--- /dev/null
+++ b/src/mainboard/hp/280_g2/devicetree.cb
@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+	}"
+
+	register "PmConfigSlpS3MinAssert"	= "SLP_S3_MIN_ASSERT_50MS"
+	register "PmConfigSlpS4MinAssert"	= "SLP_S4_MIN_ASSERT_4S"
+	register "PmConfigSlpSusMinAssert"	= "SLP_SUS_MIN_ASSERT_4S"
+	register "PmConfigSlpAMinAssert"	= "SLP_A_MIN_ASSERT_2S"
+	register "PmConfigPciClockRun"		= "1"
+	register "PmConfigPwrCycDur"		= "RESET_POWER_CYCLE_4S"
+
+	register "eist_enable" = "1"
+
+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexUart2] = PchSerialIoSkipInit,	/* Routed to debug header */
+	}"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end		# Host bridge
+		device pci 01.0 on  end		# PCIe graphics
+		device pci 02.0 on  end		# iGPU
+		device pci 08.0 on  end		# GMM
+		device pci 14.0 on		# xHCI
+			register "usb2_ports[0]"  = "USB2_PORT_MID(OC0)"
+			register "usb2_ports[1]"  = "USB2_PORT_MID(OC0)"
+			register "usb2_ports[2]"  = "USB2_PORT_MID(OC4)"
+			register "usb2_ports[3]"  = "USB2_PORT_MID(OC4)"
+			register "usb2_ports[4]"  = "USB2_PORT_MID(OC2)"
+			register "usb2_ports[5]"  = "USB2_PORT_MID(OC2)"
+			register "usb2_ports[6]"  = "USB2_PORT_MID(OC0)"
+			register "usb2_ports[7]"  = "USB2_PORT_MID(OC0)"
+			register "usb2_ports[8]"  = "USB2_PORT_MID(OC0)"
+			register "usb2_ports[9]"  = "USB2_PORT_MID(OC0)"
+			register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
+			register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
+			register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
+			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
+
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
+			register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
+			register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
+			register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+			register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+			register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+			register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
+		end
+		device pci 14.1 off end		# xDCI
+		device pci 14.2 on  end		# Thermal
+		device pci 15.0 off end		# I2C #0
+		device pci 15.1 off end		# I2C #1
+		device pci 15.2 off end		# I2C #2
+		device pci 15.3 off end		# I2C #3
+		device pci 16.0 on  end		# MEI #1
+		device pci 16.1 off end		# MEI #2
+		device pci 16.2 off end		# ME IDE-R
+		device pci 16.3 off end		# ME KT
+		device pci 16.4 off end		# MEI #3
+		device pci 17.0 on		# SATA
+			register "SataMode"		= "KBLFSP_SATA_MODE_AHCI"
+			register "SataSalpSupport"	= "1"
+			register "SataPortsEnable"	= "{
+				[0] = 1,
+				[1] = 1,
+				[2] = 1,
+				[3] = 1,
+			}"
+			register "SataPortsHotPlug"	= "{
+				[0] = 1,
+				[1] = 1,
+				[2] = 1,
+				[3] = 1,
+			}"
+			# SataPortsDevSlp not supported
+
+			# Enable test mode to allow SATA margining
+			register "SataTestMode" = "1"
+		end
+		device pci 19.0 on  end		# UART #2
+		device pci 1c.0 off end		# RP #1
+		device pci 1c.1 off end		# RP #2
+		device pci 1c.2 off end		# RP #3
+		device pci 1c.3 off end		# RP #4
+		device pci 1c.4 on		# RP #5: IT8893E PCI Bridge
+			register "PcieRpEnable[4]"			= "1"
+			register "PcieRpLtrEnable[4]"			= "1"
+			register "PcieRpAdvancedErrorReporting[4]"	= "1"
+			register "PcieRpClkSrcNumber[4]"		= "11"
+		end
+		device pci 1c.5 on		# RP #6: PCIe x1 slot
+			register "PcieRpEnable[5]"			= "1"
+			register "PcieRpHotPlug[5]"			= "1"
+			register "PcieRpLtrEnable[5]"			= "1"
+			register "PcieRpAdvancedErrorReporting[5]"	= "1"
+			register "PcieRpClkSrcNumber[5]"		= "6"
+		end
+		device pci 1c.6 on		# RP #7: RTL8111 GbE NIC
+			register "PcieRpEnable[6]"			= "1"
+			register "PcieRpLtrEnable[6]"			= "1"
+			register "PcieRpAdvancedErrorReporting[6]"	= "1"
+			register "PcieRpClkSrcNumber[6]"		= "10"
+		end
+		device pci 1c.7 on		# RP #8: M.2 2230 slot
+			register "PcieRpEnable[7]"			= "1"
+			register "PcieRpHotPlug[7]"			= "1"
+			register "PcieRpLtrEnable[7]"			= "1"
+			register "PcieRpAdvancedErrorReporting[7]"	= "1"
+			register "PcieRpClkReqSupport[7]"		= "1"
+			register "PcieRpClkReqNumber[7]"		= "6"
+			register "PcieRpClkSrcNumber[7]"		= "12"
+		end
+		device pci 1d.0 off end		# RP #9
+		device pci 1d.1 off end		# RP #10
+		device pci 1d.2 off end		# RP #11
+		device pci 1d.3 off end		# RP #12
+		device pci 1e.0 off end		# UART #0
+		device pci 1e.1 off end		# UART #1
+		device pci 1e.2 off end		# GSPI #0
+		device pci 1e.3 off end		# GSPI #1
+		device pci 1f.0 on		# LPC bridge
+			register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+			# FIXME: Missing Super I/O config
+			# register "gen1_dec" = "0x000c0291"
+		end
+		device pci 1f.1 on  end		# P2SB
+		device pci 1f.2 on  end		# PMC
+		device pci 1f.3 on  end		# Intel HDA
+		device pci 1f.4 on  end		# SMBus
+		device pci 1f.5 on  end		# SPI
+		device pci 1f.6 off end		# Intel GbE
+	end
+end
diff --git a/src/mainboard/hp/280_g2/dsdt.asl b/src/mainboard/hp/280_g2/dsdt.asl
new file mode 100644
index 0000000..b5e5a68
--- /dev/null
+++ b/src/mainboard/hp/280_g2/dsdt.asl
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/skylake/acpi/globalnvs.asl>
+
+	Device (_SB.PCI0) {
+		#include <soc/intel/skylake/acpi/systemagent.asl>
+		#include <soc/intel/skylake/acpi/pch.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/hp/280_g2/gma-mainboard.ads b/src/mainboard/hp/280_g2/gma-mainboard.ads
new file mode 100644
index 0000000..0cf02cd
--- /dev/null
+++ b/src/mainboard/hp/280_g2/gma-mainboard.ads
@@ -0,0 +1,21 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      DP3,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      eDP,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/hp/280_g2/gpio.c b/src/mainboard/hp/280_g2/gpio.c
new file mode 100644
index 0000000..9c293d7
--- /dev/null
+++ b/src/mainboard/hp/280_g2/gpio.c
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+#include "gpio.h"
+
+/* Pad configuration was generated automatically using intelp2m utility */
+static const struct pad_config gpio_table[] = {
+
+	/* ------- GPIO Community 0 ------- */
+
+	/* ------- GPIO Group GPP_A ------- */
+	_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF), 0),
+	_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)),
+	_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)),
+	_PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+	/* ------- GPIO Group GPP_B ------- */
+	_PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPO(GPP_B3, 1, DEEP),
+	_PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPO(GPP_B5, 0, PLTRST),
+	PAD_NC(GPP_B6, NONE),
+	_PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0),
+	PAD_NC(GPP_B8, NONE),
+	PAD_NC(GPP_B9, NONE),
+	PAD_NC(GPP_B10, NONE),
+	_PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(DN_20K)),
+	_PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPO(GPP_B17, 1, DEEP),
+	_PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(NF2) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(DN_20K)),
+
+	/* ------- GPIO Community 1 ------- */
+
+	/* ------- GPIO Group GPP_C ------- */
+	_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPO(GPP_C2, 1, DEEP),
+	_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_C6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_C7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C16, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C17, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C18, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_C19, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+	/* ------- GPIO Group GPP_D ------- */
+	_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D15, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D16, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_D23, NONE, PLTRST, OFF, ACPI),
+
+	/* ------- GPIO Group GPP_E ------- */
+	_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+
+	/* ------- GPIO Group GPP_F ------- */
+	_PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_F22, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F23, 1, DEEP),
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_CFG_GPO(GPP_G0, 1, PLTRST),
+	_PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPO(GPP_G2, 0, PLTRST),
+	PAD_CFG_GPO(GPP_G3, 0, PLTRST),
+	_PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_G6, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_G7, 1, DEEP),
+	_PAD_CFG_STRUCT(GPP_G8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_G9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_G10, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_G11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_G12, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_G13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_G14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPO(GPP_G15, 0, PLTRST),
+	_PAD_CFG_STRUCT(GPP_G16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_G17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_G18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_G19, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_G20, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_G21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPO(GPP_G22, 1, PLTRST),
+	PAD_CFG_GPO(GPP_G23, 1, PLTRST),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_NC(GPP_H1, NONE),
+	PAD_NC(GPP_H2, NONE),
+	PAD_NC(GPP_H3, NONE),
+	_PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_H5, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H6, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H7, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_H8, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_H9, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_H10, PAD_FUNC(GPIO) | PAD_RESET(RSMRST) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_H11, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H12, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_H14, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H15, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_H17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H18, NONE, RSMRST, LEVEL, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H19, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_H21, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, PLTRST, OFF, ACPI),
+	PAD_CFG_GPO(GPP_H23, 0, DEEP),
+
+	/* ------- GPIO Community 2 ------- */
+
+	/* -------- GPIO Group GPD -------- */
+	_PAD_CFG_STRUCT(GPD0, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	PAD_CFG_GPO(GPD1, 0, PWROK),
+	_PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)),
+	_PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)),
+	_PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	PAD_CFG_GPO(GPD7, 1, PWROK),
+	_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0),
+	PAD_CFG_GPO(GPD11, 0, PWROK),
+
+	/* ------- GPIO Community 3 ------- */
+
+	/* ------- GPIO Group GPP_I ------- */
+	_PAD_CFG_STRUCT(GPP_I0, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_I1, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_I2, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0),
+	_PAD_CFG_STRUCT(GPP_I3, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I4, NONE, PLTRST, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_I5, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_I6, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)),
+	PAD_CFG_GPI_TRIG_OWN(GPP_I7, NONE, DEEP, OFF, ACPI),
+	_PAD_CFG_STRUCT(GPP_I8, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)),
+	_PAD_CFG_STRUCT(GPP_I9, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0),
+	_PAD_CFG_STRUCT(GPP_I10, PAD_FUNC(NF1) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(DN_20K)),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/hp/280_g2/gpio.h b/src/mainboard/hp/280_g2/gpio.h
new file mode 100644
index 0000000..c3ab23c
--- /dev/null
+++ b/src/mainboard/hp/280_g2/gpio.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+void mainboard_configure_gpios(void);
diff --git a/src/mainboard/hp/280_g2/ramstage.c b/src/mainboard/hp/280_g2/ramstage.c
new file mode 100644
index 0000000..ccfd6a7
--- /dev/null
+++ b/src/mainboard/hp/280_g2/ramstage.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+	/* Configure pads prior to SiliconInit() in case there's any
+	   dependencies during hardware initialization. */
+	mainboard_configure_gpios();
+}
diff --git a/src/mainboard/hp/280_g2/romstage.c b/src/mainboard/hp/280_g2/romstage.c
new file mode 100644
index 0000000..94991a6
--- /dev/null
+++ b/src/mainboard/hp/280_g2/romstage.c
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <spd_bin.h>
+#include <soc/romstage.h>
+#include <fsp/soc_binding.h>
+
+/* Rcomp resistors are located on the CPU package */
+static const u16 rcomp_resistors[3] = { 121, 75, 100 };
+
+/* Rcomp targets for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk */
+static const u16 rcomp_targets[5] = { 50, 26, 20, 20, 26 };
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	FSP_M_CONFIG *const mem_cfg = &mupd->FspmConfig;
+
+	struct spd_block blk = {
+		.addr_map = { 0x51, 0x50 },
+	};
+
+	get_spd_smbus(&blk);
+
+	assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors));
+	assert(sizeof(mem_cfg->RcompTarget)   == sizeof(rcomp_targets));
+
+	mem_cfg->DqPinsInterleaved = true;
+
+	mem_cfg->MemorySpdDataLen = blk.len;
+	mem_cfg->MemorySpdPtr00 = (u32)blk.spd_array[0];
+	mem_cfg->MemorySpdPtr10 = (u32)blk.spd_array[1];
+
+	memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor));
+	memcpy(mem_cfg->RcompTarget,   rcomp_targets,   sizeof(mem_cfg->RcompTarget));
+
+	/* These settings are most likely useless if using a release build of FSP */
+	mem_cfg->PcdDebugInterfaceFlags = 2;	/* Enable UART */
+	mem_cfg->PcdSerialIoUartNumber  = 2;	/* Use UART #2 */
+	mem_cfg->PcdSerialDebugBaudRate = 7;	/* 115200 baud */
+	mem_cfg->PcdSerialDebugLevel    = 3;	/* Log <= Info */
+
+	/* Allow changing memory timings after MRC is done */
+	mem_cfg->RealtimeMemoryTiming = 1;
+}
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/48386
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iadf11c187307a24b15039a5a716737d9d74944e6
Gerrit-Change-Number: 48386
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons th3fanbus@gmail.com
Gerrit-MessageType: newchange



    

Change in coreboot[master]: [WIP] mb/hp/280_g2: Add new mainboard