Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32011
Change subject: soc/apl: Add devicetreee options for root ports ......................................................................
soc/apl: Add devicetreee options for root ports
List of options: - PcieRpPmSci - PcieRpTransmitterHalfSwing - PcieRpLtrMaxSnoopLatency - PcieRpLtrMaxNonSnoopLatency - PcieRpAspm
Change-Id: Ib08743f0bbf3bfaa935b153aaf161811eb148c6b Signed-off-by: Felix Singer felix.singer@9elements.com --- M src/soc/intel/apollolake/chip.c 1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32011/1
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 30a537b..8b38895 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -695,6 +695,24 @@ memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, sizeof(silconfig->PcieRpHotPlug));
+ memcpy(silconfig->PcieRpPmSci, cfg->pcie_rp_pm_sci, + sizeof(silconfig->PcieRpPmSci)); + + memcpy(silconfig->PcieRpTransmitterHalfSwing, + cfg->pcie_rp_transmitter_halfswing, + sizeof(silconfig->PcieRpTransmitterHalfSwing)); + + memcpy(silconfig->PcieRpLtrMaxSnoopLatency, + cfg->pcie_rp_ltr_max_snoop_latency, + sizeof(silconfig->PcieRpLtrMaxSnoopLatency)); + + memcpy(silconfig->PcieRpLtrMaxNonSnoopLatency, + cfg->pcie_rp_ltr_max_snoop_latency, + sizeof(silconfig->PcieRpLtrMaxNonSnoopLatency)); + + memcpy(silconfig->PcieRpAspm, cfg->pcie_rp_aspm, + sizeof(silconfig->PcieRpAspm)); + switch (cfg->serirq_mode) { case SERIRQ_QUIET: silconfig->SirqEnable = 1;
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32011
to look at the new patch set (#2).
Change subject: soc/apl: Add devicetree options for root ports ......................................................................
soc/apl: Add devicetree options for root ports
List of options: - PcieRpPmSci - PcieRpTransmitterHalfSwing - PcieRpLtrMaxSnoopLatency - PcieRpLtrMaxNonSnoopLatency - PcieRpAspm
Change-Id: Ib08743f0bbf3bfaa935b153aaf161811eb148c6b Signed-off-by: Felix Singer felix.singer@9elements.com --- M src/soc/intel/apollolake/chip.c 1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32011/2
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32011
to look at the new patch set (#3).
Change subject: soc/apl: Add devicetree options for root ports ......................................................................
soc/apl: Add devicetree options for root ports
List of options: - PcieRpPmSci - PcieRpTransmitterHalfSwing - PcieRpLtrMaxSnoopLatency - PcieRpLtrMaxNonSnoopLatency
Change-Id: Ib08743f0bbf3bfaa935b153aaf161811eb148c6b Signed-off-by: Felix Singer felix.singer@9elements.com --- M src/soc/intel/apollolake/chip.c 1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/32011/3
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32011 )
Change subject: soc/apl: Add devicetree options for root ports ......................................................................
Patch Set 7:
This change is ready for review.
Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32011 )
Change subject: soc/apl: Add devicetree options for root ports ......................................................................
Abandoned
-
Felix Singer (Code Review)