[XS] Change in coreboot[main]: soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table

[Cliff Huang (Code Review)]

Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84392?usp=email )

Change subject: soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table
......................................................................

soc/intel/common/block/acpi: Fix GPE1 blocks to ACPI FADT table

Use CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1 to add GPE1 block
rather than checking if GPE1_STS(0) is '0'.

BUG=362310295
TEST=with the flag, boot to OS and check that FADT table includes GPE1.
FADT should have:
GPE1 Block Address : 00001810
GPE1 Block Length : 18
GPE1 Base Offset : 80
Without the flag, boot to OS and check that FADT table does not include
GPE1. FADT should have:
GPE1 Block Address : 0
GPE1 Block Length : 0
GPE1 Base Offset : 0

Signed-off-by: Cliff Huang 
Change-Id: Idd8115044faff3161ea6bd1cae6c0fe8aa0ff8d7
---
M src/soc/intel/common/block/acpi/acpi.c
1 file changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/84392/1

diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index dcd4dc4..7a704f0 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -107,8 +107,9 @@
    /* GPE0 STS/EN pairs each 32 bits wide. */
    fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);

-	fadt->gpe1_blk = GPE1_STS(0) ? (pmbase + GPE1_STS(0)) : 0;
-	if (fadt->gpe1_blk) {
+	fadt->gpe1_blk = 0;
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1)) {
+		fadt->gpe1_blk = pmbase + GPE1_STS(0);
    	fadt->gpe1_blk_len = 2 * GPE1_REG_MAX * sizeof(uint32_t);
    	/*
    	 * NOTE: gpe1 is after gpe0, which has _STS and _EN register sets.