Change in coreboot[master]: mb/google/drallion: Configure LPSS controller parameters

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35638 )

Change subject: mb/google/drallion: Configure LPSS controller parameters
......................................................................

mb/google/drallion: Configure LPSS controller parameters

Change-Id: I9c57f8054f5da5add667168502ebc3e089c440f8
Signed-off-by: Aamir Bohra 
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/35638/1

diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index d824a55..e374d99 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -13,6 +13,21 @@
    register "gen2_dec" = "0x00040941" # 0x940-0x947
    register "gen3_dec" = "0x000c0951" # 0x950-0x95f

+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+		[PchSerialIoIndexSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
    # FSP configuration
    register "SaGv" = "SaGv_Enabled"
    register "HeciEnabled" = "0"

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35638 )

Change subject: mb/google/drallion: Configure LPSS controller parameters
......................................................................

Patch Set 1:

This change is ready for review.

[Aamir Bohra (Code Review)]

Hello EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Chiranjeevi Rapolu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35638

to look at the new patch set (#3).

Change subject: mb/google/drallion: Configure LPSS controller parameters
......................................................................

mb/google/drallion: Configure LPSS controller parameters

BUG=b:141575294

Change-Id: I9c57f8054f5da5add667168502ebc3e089c440f8
Signed-off-by: Aamir Bohra 
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/35638/3

[EricR Lai (Code Review)]

EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35638 )

Change subject: mb/google/drallion: Configure LPSS controller parameters
......................................................................

Patch Set 3:

I think we can disable non-used I2C, we use the 0,1,4 and 2,3,5 is not used.

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35638 )

Change subject: mb/google/drallion: Configure LPSS controller parameters
......................................................................

Patch Set 3:
> Patch Set 3:
>
> I think we can disable non-used I2C, we use the 0,1,4 and 2,3,5 is not used.

Ok, this code would set it to disable anyways.
    if (!dev || !dev->enabled)
    	return PCH_SERIAL_IO_INDEX(PchSerialIoDisabled);

[Aamir Bohra (Code Review)]

Hello EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Chiranjeevi Rapolu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35638

to look at the new patch set (#4).

Change subject: mb/google/drallion: Configure LPSS controller parameters
......................................................................

mb/google/drallion: Configure LPSS controller parameters

BUG=b:141575294

Change-Id: I9c57f8054f5da5add667168502ebc3e089c440f8
Signed-off-by: Aamir Bohra 
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/35638/4

[Aamir Bohra (Code Review)]

Hello EricR Lai, Selma Bensaid, Bora Guvendik, build bot (Jenkins), Chiranjeevi Rapolu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35638

to look at the new patch set (#5).

Change subject: mb/google/drallion: Configure LPSS controller parameters
......................................................................

mb/google/drallion: Configure LPSS controller parameters

drallion uses below LPSS controllers:

I2C: 0/1/4
GSPI: None
UART: 0(Console)

BUG=b:141575294

Change-Id: I9c57f8054f5da5add667168502ebc3e089c440f8
Signed-off-by: Aamir Bohra 
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/35638/5

[Bora Guvendik (Code Review)]

Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35638 )

Change subject: mb/google/drallion: Configure LPSS controller parameters
......................................................................

Patch Set 5: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35638 )

Change subject: mb/google/drallion: Configure LPSS controller parameters
......................................................................

mb/google/drallion: Configure LPSS controller parameters

drallion uses below LPSS controllers:

I2C: 0/1/4
GSPI: None
UART: 0(Console)

BUG=b:141575294

Change-Id: I9c57f8054f5da5add667168502ebc3e089c440f8
Signed-off-by: Aamir Bohra 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35638
Tested-by: build bot (Jenkins) 
Reviewed-by: Bora Guvendik 
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
1 file changed, 15 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Bora Guvendik: Looks good to me, approved

diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index 956e54e..2e8edd5 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -13,6 +13,21 @@
    register "gen2_dec" = "0x00040941" # 0x940-0x947
    register "gen3_dec" = "0x000c0951" # 0x950-0x95f

+	register "SerialIoDevMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
    # FSP configuration
    register "SaGv" = "SaGv_Enabled"
    register "HeciEnabled" = "0"