Change in coreboot[master]: mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board
V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48685 )
Change subject: mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board ......................................................................
mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board
This patch adds initial support for Alderlake Intel Pre-CEP board called shadowmountain.
BUG=b:175808146 TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max
Change-Id: I9cb650c88986badd6733b001d6f2a0e338421829 Signed-off-by: V Sowmya v.sowmya@intel.com --- A src/mainboard/intel/shadowmountain/Kconfig A src/mainboard/intel/shadowmountain/Kconfig.name A src/mainboard/intel/shadowmountain/board_info.txt A src/mainboard/intel/shadowmountain/dsdt.asl A src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 5 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/48685/1
diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig new file mode 100644 index 0000000..a822bcc --- /dev/null +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -0,0 +1,25 @@ +if BOARD_INTEL_SHADOWMOUNTAIN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_TABLES + select SOC_INTEL_ALDERLAKE + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config MAINBOARD_DIR + string + default "intel/shadowmountain" + +config MAINBOARD_FAMILY + string + default "Intel_shadowmountain" + +config MAINBOARD_PART_NUMBER + string + default "shadowmountain" + +endif # BOARD_INTEL_SHADOWMOUNTAIN diff --git a/src/mainboard/intel/shadowmountain/Kconfig.name b/src/mainboard/intel/shadowmountain/Kconfig.name new file mode 100644 index 0000000..6fcf21f --- /dev/null +++ b/src/mainboard/intel/shadowmountain/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_SHADOWMOUNTAIN + bool "shadowmountain" diff --git a/src/mainboard/intel/shadowmountain/board_info.txt b/src/mainboard/intel/shadowmountain/board_info.txt new file mode 100644 index 0000000..7e0cccf --- /dev/null +++ b/src/mainboard/intel/shadowmountain/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Alderlake Pre-CEP +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl new file mode 100644 index 0000000..10d08e2 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/dsdt.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ +} diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..fbd7d72 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/alderlake + device cpu_cluster 0 on + device lapic 0 on end + end +end
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48685
to look at the new patch set (#2).
Change subject: mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board ......................................................................
mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board
This patch adds initial support for Alderlake Intel Pre-CEP board called shadowmountain.
BUG=b:175808146 TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max
Change-Id: I9cb650c88986badd6733b001d6f2a0e338421829 Signed-off-by: V Sowmya v.sowmya@intel.com --- A src/mainboard/intel/shadowmountain/Kconfig A src/mainboard/intel/shadowmountain/Kconfig.name A src/mainboard/intel/shadowmountain/board_info.txt A src/mainboard/intel/shadowmountain/dsdt.asl A src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 5 files changed, 52 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/48685/2
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48685 )
Change subject: mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board ......................................................................
Patch Set 2: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48685 )
Change subject: mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board ......................................................................
Patch Set 2: Code-Review+2
Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48685 )
Change subject: mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board ......................................................................
mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board
This patch adds initial support for Alderlake Intel Pre-CEP board called shadowmountain.
BUG=b:175808146 TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max
Change-Id: I9cb650c88986badd6733b001d6f2a0e338421829 Signed-off-by: V Sowmya v.sowmya@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48685 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- A src/mainboard/intel/shadowmountain/Kconfig A src/mainboard/intel/shadowmountain/Kconfig.name A src/mainboard/intel/shadowmountain/board_info.txt A src/mainboard/intel/shadowmountain/dsdt.asl A src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb 5 files changed, 52 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig new file mode 100644 index 0000000..a822bcc --- /dev/null +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -0,0 +1,25 @@ +if BOARD_INTEL_SHADOWMOUNTAIN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_TABLES + select SOC_INTEL_ALDERLAKE + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config MAINBOARD_DIR + string + default "intel/shadowmountain" + +config MAINBOARD_FAMILY + string + default "Intel_shadowmountain" + +config MAINBOARD_PART_NUMBER + string + default "shadowmountain" + +endif # BOARD_INTEL_SHADOWMOUNTAIN diff --git a/src/mainboard/intel/shadowmountain/Kconfig.name b/src/mainboard/intel/shadowmountain/Kconfig.name new file mode 100644 index 0000000..e489039 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_SHADOWMOUNTAIN + bool "shadowmountain" diff --git a/src/mainboard/intel/shadowmountain/board_info.txt b/src/mainboard/intel/shadowmountain/board_info.txt new file mode 100644 index 0000000..7e0cccf --- /dev/null +++ b/src/mainboard/intel/shadowmountain/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Alderlake Pre-CEP +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl new file mode 100644 index 0000000..10d08e2 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/dsdt.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ +} diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..fbd7d72 --- /dev/null +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/alderlake + device cpu_cluster 0 on + device lapic 0 on end + end +end
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Hung-Te Lin (Code Review) -
Subrata Banik (Code Review)
-
Tim Wawrzynczak (Code Review)
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V Sowmya (Code Review)