Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s

[Kevin Chang (Code Review)]

Attention is currently required from: Peichao Wang, Tim Wawrzynczak.
Hello build bot (Jenkins), Peichao Wang, Tim Wawrzynczak,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/62919

to look at the new patch set (#9).

Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
......................................................................

mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s

GL9763e didn't support L0s state that disable L0s at root port.

BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.

Signed-off-by: Kevin Chang 
Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988
---
M src/mainboard/google/brya/variants/taeko/overridetree.cb
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
3 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/62919/9