Change in coreboot[master]: soc/intel/common/graphics: Add new Kconfig SOC_INTEL_DISABLE_IGD

[Nico Huber (Code Review)]

Attention is currently required from: Subrata Banik, Angel Pons, Patrick Rudolph.
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49470 )

Change subject: soc/intel/common/graphics: Add new Kconfig SOC_INTEL_DISABLE_IGD
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Patch Set 3: Code-Review+1

(2 comments)

Patchset:

PS3: 
I've been thinking where this requirement to fully disable
the IGD might derive from, and found something that goes
fundamentally wrong with the soc/intel/ code. The default
of ONBOARD_VGA_IS_PRIMARY is `n`. However, all the chipset
code since Broadwell ignores that setting. The PCI driver
for the IGD is supposed to disable VGA decoding (or the
whole device) when `.disable` gets called. But `.disable`
is not implemented.

With a DGPU present and the default `n` that means one
thing: resource conflict. The IGPU decodes VGA cycles
and the generic code in `src/device/device.c` configures
bridges to route them to the DGPU too.

I don't have all the hardware to test and definitely not
the patience to look into the code of half a dozen FSPs.
So I would highly appreciate if Intel could look into the
implementation of `.disable` for the IGD.

File src/soc/intel/common/block/graphics/Kconfig:

https://review.coreboot.org/c/coreboot/+/49470/comment/096411f4_88dcd9e5 
PS3, Line 12: 	bool "Skip IGD Initialization"
Technically, it's not skipping but actively disabling it.