[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge

[Patrick Rudolph (Code Review)]

Attention is currently required from: Angel Pons.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79784?usp=email )

Change subject: nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge
......................................................................

nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge

On Sandy Bridge the MRC.bin sets bit SRT in register
TC_MR2_SHADOW as well as it's currently done on Ivy Bridge.

Tested on Lenovo X220: Still boots and works fine.

Change-Id: Id2773d3ae8c6c48193a23174086f62617335a7af
Signed-off-by: Patrick Rudolph 
---
M src/northbridge/intel/sandybridge/raminit_common.c
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79784/1

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 16751b9..2033043 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -783,6 +783,8 @@
    int srt = 0;
    if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ)
    	srt = dimm->flags.ext_temp_refresh && !dimm->flags.asr;
+	else if (IS_SANDY_CPU(ctrl->cpu))
+		srt = dimm->flags.ext_temp_refresh && !dimm->flags.asr;

u16 mr2reg = 0;
    mr2reg |= pasr;