Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Move and rename ARCH_STAGE_HAS_xxx_SECTION rules
Currently only x86 requires special handling here, for simplicity avoid introducing <arch/rules.h> and deal with this directly in <rules.h>.
For consistency prefixes are changed from ARCH_ to ENV_.
The new definition of ENV_STAGE_HAS_HEAP_SECTION is changed to reflect whether our build for the stage includes implementation of malloc().
Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/include/arch/memlayout.h M src/include/memlayout.h M src/include/rules.h M src/lib/program.ld 4 files changed, 16 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/35014/1
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index de80f42..7dcdd98 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -16,13 +16,6 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H
- -#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE -/* No .data or .bss sections. Cache as RAM is handled separately. */ -#define ARCH_STAGE_HAS_DATA_SECTION 0 -#define ARCH_STAGE_HAS_BSS_SECTION 0 -#endif - #if (CONFIG_RAMTOP == 0) # error "CONFIG_RAMTOP not configured" #endif diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 1ed87b6..505ccc1 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -30,24 +30,6 @@ #define ARCH_CACHELINE_ALIGN_SIZE 64 #endif
-/* Default to data as well as bss. */ -#ifndef ARCH_STAGE_HAS_DATA_SECTION -#define ARCH_STAGE_HAS_DATA_SECTION 1 -#endif - -#ifndef ARCH_STAGE_HAS_BSS_SECTION -#define ARCH_STAGE_HAS_BSS_SECTION 1 -#endif - -/* - * Default is that currently ENV_PAYLOAD_LOADER enable stage, smm, - * and rmodules have a heap. - */ -#ifndef ARCH_STAGE_HAS_HEAP_SECTION -#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_PAYLOAD_LOADER || ENV_SMM || \ - ENV_RMODULE) -#endif - #define STR(x) #x
#define ALIGN_COUNTER(align) \ diff --git a/src/include/rules.h b/src/include/rules.h index 10cd715..3412e01 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -266,6 +266,19 @@ #define ENV_PAYLOAD_LOADER ENV_RAMSTAGE #endif
+#if CONFIG(ARCH_X86) && (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE) +/* No .data or .bss sections. Cache as RAM is handled separately. */ +#define ENV_STAGE_HAS_DATA_SECTION 0 +#define ENV_STAGE_HAS_BSS_SECTION 0 +#else +/* Both .data nnd .bss, sometimes SRAM not DRAM. */ +#define ENV_STAGE_HAS_DATA_SECTION 1 +#define ENV_STAGE_HAS_BSS_SECTION 1 +#endif + +/* Currently ramstage and smm build with malloc().*/ +#define ENV_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM) + /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. The reason diff --git a/src/lib/program.ld b/src/lib/program.ld index 851aa75..1b30c0e 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -85,7 +85,7 @@ #endif
/* Include data, bss, and heap in that order. Not defined for all stages. */ -#if ARCH_STAGE_HAS_DATA_SECTION +#if ENV_STAGE_HAS_DATA_SECTION .data . : { . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); _data = .; @@ -125,7 +125,7 @@ } #endif
-#if ARCH_STAGE_HAS_BSS_SECTION +#if ENV_STAGE_HAS_BSS_SECTION .bss . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; @@ -138,7 +138,7 @@ } #endif
-#if ARCH_STAGE_HAS_HEAP_SECTION +#if ENV_STAGE_HAS_HEAP_SECTION .heap . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _heap = .;
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35014/1/src/include/rules.h File src/include/rules.h:
https://review.coreboot.org/c/coreboot/+/35014/1/src/include/rules.h@280 PS1, Line 280: ENV_RAMSTAGE Shouldn't this be ENV_PAYLOAD_LOADER to keep it the same as before this change?
https://review.coreboot.org/c/coreboot/+/35014/1/src/include/rules.h@280 PS1, Line 280: ) Why was ENV_RMODULE dropped here?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35014/1/src/include/rules.h File src/include/rules.h:
https://review.coreboot.org/c/coreboot/+/35014/1/src/include/rules.h@280 PS1, Line 280: )
Why was ENV_RMODULE dropped here?
I got it wrong and need to but it back :/
https://review.coreboot.org/c/coreboot/+/35014/1/src/include/rules.h@280 PS1, Line 280: ENV_RAMSTAGE
Shouldn't this be ENV_PAYLOAD_LOADER to keep it the same as before this change?
With RAMPAYLOAD=y you would just add heap section without malloc() for postcar. I am not so confinced if we should add postcar-y += malloc.c, but that's not the scope here.
See late CB:32725 commentary.
Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35014
to look at the new patch set (#2).
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Move and rename ARCH_STAGE_HAS_xxx_SECTION rules
Currently only x86 requires special handling here, for simplicity avoid introducing <arch/rules.h> and deal with this directly in <rules.h>.
For consistency prefixes are changed from ARCH_ to ENV_.
Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/include/arch/memlayout.h M src/include/memlayout.h M src/include/rules.h M src/lib/program.ld 4 files changed, 16 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/35014/2
Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35014
to look at the new patch set (#4).
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Move and rename ARCH_STAGE_HAS_xxx_SECTION rules
Currently only x86 requires special handling here, for simplicity avoid introducing <arch/rules.h> and deal with this directly in <rules.h>.
For consistency prefixes are changed from ARCH_ to ENV_.
Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/include/arch/memlayout.h M src/include/memlayout.h M src/include/rules.h M src/lib/program.ld 4 files changed, 16 insertions(+), 28 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/35014/4
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35014/1/src/include/rules.h File src/include/rules.h:
https://review.coreboot.org/c/coreboot/+/35014/1/src/include/rules.h@280 PS1, Line 280: )
I got it wrong and need to but it back :/
Done
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35014/4/src/include/rules.h File src/include/rules.h:
https://review.coreboot.org/c/coreboot/+/35014/4/src/include/rules.h@270 PS4, Line 270: /* No .data or .bss sections. Cache as RAM is handled separately. */ Append the comment to refer to the file which handles that? arch/x86/car.ld I know it wasn't there before, but we could provide a hint in the comments. And we may want to drop a hint somewhere that lib/program.ld isn't used for many of these programs on x86.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35014/1/src/include/rules.h File src/include/rules.h:
https://review.coreboot.org/c/coreboot/+/35014/1/src/include/rules.h@280 PS1, Line 280: ENV_RAMSTAGE
With RAMPAYLOAD=y you would just add heap section without malloc() for postcar. […]
Ah interesting. Thanks for the pointer.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 4: Code-Review+1
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35014/4/src/include/rules.h File src/include/rules.h:
https://review.coreboot.org/c/coreboot/+/35014/4/src/include/rules.h@270 PS4, Line 270: /* No .data or .bss sections. Cache as RAM is handled separately. */
Append the comment to refer to the file which handles that? arch/x86/car. […]
Looking at x86/memlayout.ld, it includes <memlayout.h> which includes <xx/program.ld> via BOOTBLOCK(), VERSTAGE() and ROMSTAGE() macros?
https://review.coreboot.org/c/coreboot/+/35014/4/src/lib/program.ld File src/lib/program.ld:
https://review.coreboot.org/c/coreboot/+/35014/4/src/lib/program.ld@129 PS4, Line 129: .bss . : { Not good.. .bss ends up inside execute-in-place bootblock with CB:35003.
Idx Name Size VMA LMA File off Algn 0 .text 00001fd8 ffffc000 ffffc000 00001000 2**12 CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE 1 .bss 00000010 ffffdfd8 ffffdfd8 00002fd8 2**2 ALLOC 2 .car.data 00002e50 fefc0000 fefc0000 00000000 2**0 ALLOC
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35014/4/src/lib/program.ld File src/lib/program.ld:
https://review.coreboot.org/c/coreboot/+/35014/4/src/lib/program.ld@128 PS4, Line 128: #if ENV_STAGE_HAS_BSS_SECTION #if ENV_STAGE_HAS_BSS_SECTION && !ENV_CACHE_AS_RAM ?
https://review.coreboot.org/c/coreboot/+/35014/4/src/lib/program.ld@141 PS4, Line 141: #if ENV_STAGE_HAS_HEAP_SECTION likewise
Hello Aaron Durbin, Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35014
to look at the new patch set (#5).
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Move and rename ARCH_STAGE_HAS_xxx_SECTION rules
Currently only x86 requires special handling here, for simplicity avoid introducing <arch/rules.h> and deal with this directly in <rules.h>.
For consistency prefixes are changed from ARCH_ to ENV_.
Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/include/arch/memlayout.h M src/include/memlayout.h M src/include/rules.h M src/lib/program.ld 4 files changed, 20 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/35014/5
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 5:
(3 comments)
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35014/4/src/lib/program.ld File src/lib/program.ld:
https://review.coreboot.org/c/coreboot/+/35014/4/src/lib/program.ld@128 PS4, Line 128: #if ENV_STAGE_HAS_BSS_SECTION
#if ENV_STAGE_HAS_BSS_SECTION && !ENV_CACHE_AS_RAM ?
CB:35016
https://review.coreboot.org/c/coreboot/+/35014/4/src/lib/program.ld@129 PS4, Line 129: .bss . : {
Not good.. .bss ends up inside execute-in-place bootblock with CB:35003. […]
Ack
https://review.coreboot.org/c/coreboot/+/35014/4/src/lib/program.ld@141 PS4, Line 141: #if ENV_STAGE_HAS_HEAP_SECTION
likewise
Ack
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h File src/include/rules.h:
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h@277 PS5, Line 277: sometimes SRAM not DRAM Doesn't this comment apply only to PRE_RAM stages?
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h@278 PS5, Line 278: #define ENV_STAGE_HAS_DATA_SECTION 1 : #define ENV_STAGE_HAS_BSS_SECTION 1 Can these be moved out of #if .. #else .. #endif and defined as !ENV_CACHE_AS_RAM always?
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h@288 PS5, Line 288: he reason : * post-CAR utilizes __SIMPLE_DEVICE__ is for simplicity. Currently there's : * no known requirement that devicetree would be needed during that stage. Not for this change, but this comment needs an update. Introduction of ENV_PAYLOAD_LOADER has changed the behavior here if post-CAR is the payload loader.
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h@297 PS5, Line 297: defined(__PRE_RAM__) Should this be updated to ENV_CACHE_AS_RAM as well may be in a follow-up CL?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h File src/include/rules.h:
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h@297 PS5, Line 297: defined(__PRE_RAM__)
Should this be updated to ENV_CACHE_AS_RAM as well may be in a follow-up CL?
I see this is already done in a follow-up CL.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h File src/include/rules.h:
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h@277 PS5, Line 277: sometimes SRAM not DRAM
Doesn't this comment apply only to PRE_RAM stages?
Wording "sometimes" does not define when exactly one changes from SRAM to DRAM. Unlike Julius mentioned, I did not notice places where ARM code would exactly care about backing store in SRAM or DRAM. Maybe such distinction and this comment can be discussed in CB:34982?
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h@278 PS5, Line 278: #define ENV_STAGE_HAS_DATA_SECTION 1 : #define ENV_STAGE_HAS_BSS_SECTION 1
Can these be moved out of #if .. #else .. […]
CB:35016 and CB:35004 will touch these, making it more complex than !ENV_CACHE_AS_RAM for ARCH_X86. I wanted to keep !ARCH_X86 case clean.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 5: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Patch Set 5:
(3 comments)
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h File src/include/rules.h:
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h@277 PS5, Line 277: sometimes SRAM not DRAM
Wording "sometimes" does not define when exactly one changes from SRAM to DRAM. […]
Ack
https://review.coreboot.org/c/coreboot/+/35014/5/src/include/rules.h@278 PS5, Line 278: #define ENV_STAGE_HAS_DATA_SECTION 1 : #define ENV_STAGE_HAS_BSS_SECTION 1
CB:35016 and CB:35004 will touch these, making it more complex than !ENV_CACHE_AS_RAM for ARCH_X86. […]
Ack
https://review.coreboot.org/c/coreboot/+/35014/4/src/include/rules.h File src/include/rules.h:
https://review.coreboot.org/c/coreboot/+/35014/4/src/include/rules.h@270 PS4, Line 270: /* No .data or .bss sections. Cache as RAM is handled separately. */
Looking at x86/memlayout.ld, it includes <memlayout.h> which includes <xx/program. […]
Done
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35014 )
Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules ......................................................................
Move and rename ARCH_STAGE_HAS_xxx_SECTION rules
Currently only x86 requires special handling here, for simplicity avoid introducing <arch/rules.h> and deal with this directly in <rules.h>.
For consistency prefixes are changed from ARCH_ to ENV_.
Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35014 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org --- M src/arch/x86/include/arch/memlayout.h M src/include/memlayout.h M src/include/rules.h M src/lib/program.ld 4 files changed, 20 insertions(+), 36 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h index de80f42..7dcdd98 100644 --- a/src/arch/x86/include/arch/memlayout.h +++ b/src/arch/x86/include/arch/memlayout.h @@ -16,13 +16,6 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H
- -#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE -/* No .data or .bss sections. Cache as RAM is handled separately. */ -#define ARCH_STAGE_HAS_DATA_SECTION 0 -#define ARCH_STAGE_HAS_BSS_SECTION 0 -#endif - #if (CONFIG_RAMTOP == 0) # error "CONFIG_RAMTOP not configured" #endif diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 1ed87b6..505ccc1 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -30,24 +30,6 @@ #define ARCH_CACHELINE_ALIGN_SIZE 64 #endif
-/* Default to data as well as bss. */ -#ifndef ARCH_STAGE_HAS_DATA_SECTION -#define ARCH_STAGE_HAS_DATA_SECTION 1 -#endif - -#ifndef ARCH_STAGE_HAS_BSS_SECTION -#define ARCH_STAGE_HAS_BSS_SECTION 1 -#endif - -/* - * Default is that currently ENV_PAYLOAD_LOADER enable stage, smm, - * and rmodules have a heap. - */ -#ifndef ARCH_STAGE_HAS_HEAP_SECTION -#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_PAYLOAD_LOADER || ENV_SMM || \ - ENV_RMODULE) -#endif - #define STR(x) #x
#define ALIGN_COUNTER(align) \ diff --git a/src/include/rules.h b/src/include/rules.h index 10cd715..ed14722 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -266,6 +266,23 @@ #define ENV_PAYLOAD_LOADER ENV_RAMSTAGE #endif
+#if CONFIG(ARCH_X86) +/* Indicates memory layout is determined by arch/x86/car.ld. */ +#define ENV_CACHE_AS_RAM (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE) +/* No .data sections with execute-in-place from ROM. */ +#define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM +/* No .bss sections with execute-in-place from ROM. */ +#define ENV_STAGE_HAS_BSS_SECTION !ENV_CACHE_AS_RAM +#else +/* Both .data and .bss, sometimes SRAM not DRAM. */ +#define ENV_STAGE_HAS_DATA_SECTION 1 +#define ENV_STAGE_HAS_BSS_SECTION 1 +#define ENV_CACHE_AS_RAM 0 +#endif + +/* Currently rmodules, ramstage and smm have heap. */ +#define ENV_STAGE_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM) + /** * For pre-DRAM stages and post-CAR always build with simple device model, ie. * PCI, PNP and CPU functions operate without use of devicetree. The reason @@ -281,12 +298,4 @@ #define __SIMPLE_DEVICE__ #endif
-/* x86 specific. Indicates that the current stage is running with cache-as-ram - * enabled from the beginning of the stage in C code. */ -#if defined(__PRE_RAM__) -#define ENV_CACHE_AS_RAM CONFIG(ARCH_X86) -#else -#define ENV_CACHE_AS_RAM 0 -#endif - #endif /* _RULES_H */ diff --git a/src/lib/program.ld b/src/lib/program.ld index 851aa75..1b30c0e 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -85,7 +85,7 @@ #endif
/* Include data, bss, and heap in that order. Not defined for all stages. */ -#if ARCH_STAGE_HAS_DATA_SECTION +#if ENV_STAGE_HAS_DATA_SECTION .data . : { . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); _data = .; @@ -125,7 +125,7 @@ } #endif
-#if ARCH_STAGE_HAS_BSS_SECTION +#if ENV_STAGE_HAS_BSS_SECTION .bss . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; @@ -138,7 +138,7 @@ } #endif
-#if ARCH_STAGE_HAS_HEAP_SECTION +#if ENV_STAGE_HAS_HEAP_SECTION .heap . : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _heap = .;
-
Aaron Durbin (Code Review) -
Furquan Shaikh (Code Review)
-
Julius Werner (Code Review)
-
Kyösti Mälkki (Code Review)