Change in coreboot[master]: soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Furquan Shaikh, Subrata Banik, Patrick Rudolph, EricR Lai.
Hello build bot (Jenkins), Furquan Shaikh, Subrata Banik, Patrick Rudolph, EricR Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/51460

to look at the new patch set (#2).

Change subject: soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources
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soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources

The Intel ADL BIOS specification #627270 recommends reserving the
following resources for each PCIe TBT root port:
 - 42 buses
 - 192 MiB Non-prefetchable memory
 - 448 MiB Prefetchable memory

Add a mainboard Kconfig which will auto-select these recommended values,
in addition to PCIEXP_HOTPLUG.

Signed-off-by: Tim Wawrzynczak 
Change-Id: Icdfa2688d69c2db0f98d0523d5aba42eec1824db
---
M src/soc/intel/alderlake/Kconfig
1 file changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/51460/2