Change in coreboot[master]: soc/intel/cannonlake: add files

[Nick Vaccaro (Code Review)]

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/21283

Change subject: soc/intel/cannonlake: add files
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soc/intel/cannonlake: add files

Add some files to the build.

Change-Id: I4931f6c6f089cc54ea168cf4a80d268d983a61de
Signed-off-by: Nick Vaccaro 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/21283/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 65b581e..85d94f6 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -16,6 +16,7 @@
    select BOOT_DEVICE_SUPPORTS_WRITES
    select C_ENVIRONMENT_BOOTBLOCK
    select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+	select GENERIC_GPIO_LIB
    select HAVE_HARD_RESET
    select HAVE_INTEL_FIRMWARE
    select HAVE_MONOTONIC_TIMER
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 0c05057..dba04a8 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -19,6 +19,7 @@
 bootblock-y += spi.c
 bootblock-$(CONFIG_UART_DEBUG) += uart.c

+romstage-y += gpio.c
 romstage-y += gspi.c
 romstage-y += memmap.c
 romstage-y += pmutil.c
@@ -28,6 +29,7 @@

ramstage-y += chip.c
 ramstage-y += cpu.c
+ramstage-y += gpio.c
 ramstage-y += gspi.c
 ramstage-y += memmap.c
 ramstage-y += pmutil.c
@@ -42,6 +44,9 @@
 postcar-y += spi.c
 postcar-$(CONFIG_UART_DEBUG) += uart.c

+verstage-y += gspi.c
+verstage-y += spi.c
+
 CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20
 CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/cannonlake