[XS] Change in coreboot[main]: mb/google/brya/constitution: Enable RTD3 for SSD to resolve S0ix issue

[Pranava Y N (Code Review)]

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86686?usp=email )

Change subject: mb/google/brya/constitution: Enable RTD3 for SSD to resolve S0ix issue
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mb/google/brya/constitution: Enable RTD3 for SSD to resolve S0ix issue

Add PCIe RTD3 support so NVMe gets placed into D3 state when entering
S0ix. Some SSDs block the CPU from reaching C10 during the S0ix
suspend without the RTD3 configuration.

BUG=b:391612392
TEST=Run suspend_stress_test on constitution device and verify that
the device suspends to S0ix.

Change-Id: Ia367911d6d55b1f769c1660a6f42118988975621
Signed-off-by: Pranava Y N 
---
M src/mainboard/google/brya/variants/constitution/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/86686/1

diff --git a/src/mainboard/google/brya/variants/constitution/overridetree.cb b/src/mainboard/google/brya/variants/constitution/overridetree.cb
index 01e4a15..f6c5380 100644
--- a/src/mainboard/google/brya/variants/constitution/overridetree.cb
+++ b/src/mainboard/google/brya/variants/constitution/overridetree.cb
@@ -145,6 +145,13 @@
    			.clk_src = 0,
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "is_storage" = "true"
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F14)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
+				register "srcclk_pin" = "0"
+				device generic 0 on end
+			end
    	end
    	device ref tcss_dma0 on
    		chip drivers/intel/usb4/retimer