[S] Change in coreboot[main]: soc/intel/alderlake: Optimize reset handling for non-UFS boot
Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro.
Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84996?usp=email )
Change subject: soc/intel/alderlake: Optimize reset handling for non-UFS boot ......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/romstage/romstage.c:
https://review.coreboot.org/c/coreboot/+/84996/comment/7bec0fcd_3762d3b1?usp... : PS1, Line 200: if (ps->prev_sleep_state == ACPI_S5 && !mainboard_expects_another_reset()) {
When you come out of global_reset, is the previous state S5? If not, then we will never end up disabling UFS.
Atleast on my testing, the previous sleep state is not showing as S5.
␛[0m[INFO ] cse_lite: Set Boot Partition Info Command (RW)␛[0m ␛[0m[DEBUG] HECI: Global Reset(Type:1) Command␛[0m ␀␛[0m ␛[0m ␛[1m[NOTE ] coreboot-v1.9308_26_0.0.22-38623-g629ff30d2834 Sat Oct 19 18:42:55 UTC 2024 x86_32 romstage starting (log level: 8)...␛[0m ␛[0m[DEBUG] pm1_sts: 8000 pm1_en: 0000 pm1_cnt: 00000000␛[0m ␛[0m[DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000␛[0m ␛[0m[DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000␛[0m ␛[0m[DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000␛[0m ␛[0m[DEBUG] gpe0_sts[3]: 00014040 gpe0_en[3]: 00000000␛[0m ␛[0m[DEBUG] TCO_STS: 0000 0000␛[0m ␛[0m[DEBUG] GEN_PMCON: d9801038 00002200␛[0m ␛[0m[DEBUG] GBLRST_CAUSE: 00000040 00000000␛[0m ␛[0m[DEBUG] HPR_CAUSE0: 00000000␛[0m ␛[0m[DEBUG] prev_sleep_state 0 (S0)␛[0m
post global reset, we should see sleep state as S5. There were some bug reported previously where the sleep states are not working as expected. Details https://review.coreboot.org/c/coreboot/+/72053 and https://b.corp.google.com/issues/265939425#comment38
Trulo:
``` [NOTE ] coreboot-coreboot-unknown.9999.ea4a128 Sun Nov 3 05:55:26 UTC 2024 ramstage starting (log level: 8)... [DEBUG] Normal boot [DEBUG] FMAP: area RW_MRC_CACHE found @ 84d000 (65536 bytes) [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. [INFO ] MMAP window: SPI flash base=0x3a0000, Host base=0xff3a0000, Size=0xc60000 [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 [NOTE ] MRC: no data in 'RW_MRC_CACHE' [DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update. [DEBUG] MRC: updated 'RW_MRC_CACHE'. [DEBUG] FMAP: area RW_ELOG found @ 85d000 (4096 bytes) [INFO ] ELOG: NV offset 0x85d000 size 0x1000 [INFO ] ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 [INFO ] ELOG: Event(17) added with size 13 at 2024-10-16 00:35:35 UTC [INFO ] ELOG: Event(AA) added with size 11 at 2024-10-16 00:35:35 UTC [INFO ] Probing TPM I2C: done! DID_VID 0x504a6666 [INFO ] Locality already claimed [DEBUG] cr50 TPM 2.0 (i2c 0:0x50 id 0x504a) [INFO ] VB2:vb2_digest_init() 63176 bytes, hash algo 2, HW acceleration enabled [INFO ] src/security/tpm/tss/tcg-2.0/tss.c:253 index 0x100d return code 0x0 [INFO ] tlcl_write: response is 0x0 [INFO ] MRC: TPM MRC hash idx 0x100d updated successfully. [DEBUG] BS: BS_PRE_DEVICE entry times (exec / console): 95 / 123 ms [INFO ] Reserved BERT region base: 0x7688e000, size: 0x10000 [DEBUG] cse_lite: Number of partitions = 3 [DEBUG] cse_lite: Current partition = RO [DEBUG] cse_lite: Next partition = RO [DEBUG] cse_lite: Flags = 0x3 [DEBUG] cse_lite: RO version = 16.50.15.1515 (Status=0x0, Start=0x2000, End=0x144fff) [DEBUG] cse_lite: RW version = 16.50.15.1515 (Status=0x0, Start=0x1af000, End=0x39cfff) [DEBUG] rt_debug: dbg_feature_cntrl.cse_fw_update_disable=0 [DEBUG] FMAP: area SI_ME found @ 1000 (3796992 bytes) [DEBUG] cse_lite: CSE RW partition: offset = 0x1af000, size = 0x1ee000 [DEBUG] FMAP: area FW_MAIN_A found @ 3a2000 (2312128 bytes) [INFO ] CBFS: Found 'me_rw.version' @0x78e80 size 0xe in mcache @0x769dd35c [INFO ] VB2:vb2_digest_init() 14 bytes, hash algo 2, HW acceleration enabled [DEBUG] cse_lite: CSE CBFS RW version : 16.50.15.1515 [INFO ] cse_lite: Set Boot Partition Info Command (RW) [DEBUG] HECI: Global Reset(Type:1) Command
... ...
[NOTE ] coreboot-coreboot-unknown.9999.ea4a128 Sun Nov 3 05:55:26 UTC 2024 romstage starting (log level: 8)... [DEBUG] pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00001c00 [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 [DEBUG] gpe0_sts[3]: 00010000 gpe0_en[3]: 00082000 [DEBUG] TCO_STS: 0000 0000 [DEBUG] GEN_PMCON: d1801038 00002200 [DEBUG] GBLRST_CAUSE: 00000040 00000000 [DEBUG] HPR_CAUSE0: 00000000 [DEBUG] prev_sleep_state 5 [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 [INFO ] TXT disabled successfully - Unlocked memory [INFO ] FW_CONFIG value from CBI is 0x20000005 [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! ```
Brox:
``` [NOTE ] coreboot-coreboot-unknown.9999.fa84db0 Tue Nov 05 14:51:43 UTC 2024 x86_32 romstage starting (log level: 8)... [DEBUG] pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 [DEBUG] gpe0_sts[3]: 00010000 gpe0_en[3]: 00080000 [DEBUG] TCO_STS: 0000 0000 [DEBUG] GEN_PMCON: d0015038 00002200 [DEBUG] GBLRST_CAUSE: 00000000 00000000 [DEBUG] HPR_CAUSE0: 00000000 [DEBUG] prev_sleep_state 5 (S5) [INFO ] OC Watchdog: disabling watchdog timer [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 [INFO ] TXT disabled successfully - Unlocked memory [INFO ] FW_CONFIG value from CBI is 0x12a [DEBUG] cse_lite: Number of partitions = 3 [DEBUG] cse_lite: Current partition = RO [DEBUG] cse_lite: Next partition = RO [DEBUG] cse_lite: Flags = 0x3 [DEBUG] cse_lite: RO version = 16.1.35.2557 (Start=0x2000, End=0x19bfff) [DEBUG] cse_lite: RW version = 16.1.35.2557 (Start=0x205000, End=0x449fff) [DEBUG] rt_debug: dbg_feature_cntrl.cse_fw_update_disable=255 [DEBUG] FMAP: area SI_ME found @ 1000 (5238784 bytes) [DEBUG] cse_lite: CSE RW partition: offset = 0x205000, size = 0x245000 [DEBUG] FMAP: area FW_MAIN_A found @ 510000 (8323008 bytes) [INFO ] Fixed Decode Window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 [INFO ] Extended Decode Window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 [INFO ] CBFS: Found 'me_rw.version' @0x92d40 size 0xd in mcache @0xfef9155c [INFO ] VB2:vb2_digest_init() 13 bytes, hash algo 2, HW acceleration enabled [DEBUG] cse_lite: CSE CBFS RW version : 16.1.35.2557 [INFO ] cse_lite: Set Boot Partition Info Command (RW) [DEBUG] HECI: Global Reset(Type:1) Command
... ...
[NOTE ] coreboot-coreboot-unknown.9999.fa84db0 Tue Nov 05 14:51:43 UTC 2024 x86_32 romstage starting (log level: 8)... [DEBUG] pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00001c00 [DEBUG] gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 [DEBUG] gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 [DEBUG] gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 [DEBUG] gpe0_sts[3]: 00010000 gpe0_en[3]: 00080000 [DEBUG] TCO_STS: 0000 0000 [DEBUG] GEN_PMCON: d1001038 00002200 [DEBUG] GBLRST_CAUSE: 00000040 00000000 [DEBUG] HPR_CAUSE0: 00000000 [DEBUG] prev_sleep_state 5 (S5) [INFO ] OC Watchdog: disabling watchdog timer [INFO ] SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 [INFO ] TXT disabled successfully - Unlocked memory [INFO ] FW_CONFIG value from CBI is 0x12a [DEBUG] cse_lite: Number of partitions = 3 [DEBUG] cse_lite: Current partition = RW [DEBUG] cse_lite: Next partition = RW [DEBUG] cse_lite: Flags = 0x3 [DEBUG] cse_lite: RO version = 16.1.35.2557 (Start=0x2000, End=0x19bfff) [DEBUG] cse_lite: RW version = 16.1.35.2557 (Start=0x205000, End=0x449fff) [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! ```
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Subrata Banik (Code Review)