Change in coreboot[master]: soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48660 )

Change subject: soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES
......................................................................

soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES

Change-Id: I42ddea2c04bf1ecb2466db3d56d15d51bda486c8
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/48660/1

diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index de29dea..39d8517 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -225,8 +225,8 @@
    configure_dpr(dev);
    union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
    if (dpr.size) {
-		uint32_t dpr_base_k = (dpr.top - dpr.size) << 10;
-		uint32_t dpr_size_k = dpr.size << 10;
+		uint64_t dpr_base_k = (dpr.top - dpr.size) << 10;
+		uint64_t dpr_size_k = dpr.size << 10;
    	reserved_ram_resource(dev, index++, dpr_base_k, dpr_size_k);
    	LOG_MEM_RESOURCE("dpr", dev, index, dpr_base_k, dpr_size_k);
    }

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48660 )

Change subject: soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES
......................................................................

Patch Set 1: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/48660/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/48660/1//COMMIT_MSG@7 
PS1, Line 7: soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES
Please add a config to build-test the code with this option. I usually select multiple options to improve coverage. Some example changes I've done: CB:43977 CB:45974 CB:48546

[Marc Jones (Code Review)]

Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48660 )

Change subject: soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES
......................................................................

Patch Set 1: Code-Review+2

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48660 )

Change subject: soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48660/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/48660/1//COMMIT_MSG@7 
PS1, Line 7: soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES
> Please add a config to build-test the code with this option. I usually select multiple options to improve coverage. Some example changes I've done: CB:43977 CB:45974 CB:48546

Done in https://review.coreboot.org/c/coreboot/+/48675

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48660 )

Change subject: soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES
......................................................................

soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES

Change-Id: I42ddea2c04bf1ecb2466db3d56d15d51bda486c8
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48660
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Marc Jones 
---
M src/soc/intel/xeon_sp/uncore.c
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marc Jones: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c
index 8965b3b..00623a8 100644
--- a/src/soc/intel/xeon_sp/uncore.c
+++ b/src/soc/intel/xeon_sp/uncore.c
@@ -230,8 +230,8 @@
    configure_dpr(dev);
    union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
    if (dpr.size) {
-		uint32_t dpr_base_k = (dpr.top - dpr.size) << 10;
-		uint32_t dpr_size_k = dpr.size << 10;
+		uint64_t dpr_base_k = (dpr.top - dpr.size) << 10;
+		uint64_t dpr_size_k = dpr.size << 10;
    	reserved_ram_resource(dev, index++, dpr_base_k, dpr_size_k);
    	LOG_MEM_RESOURCE("dpr", dev, index, dpr_base_k, dpr_size_k);
    }