Change in coreboot[master]: soc/amd/stoneyridge/fch: add GNVS-related TODOs

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60196 )

Change subject: soc/amd/stoneyridge/fch: add GNVS-related TODOs
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soc/amd/stoneyridge/fch: add GNVS-related TODOs

The AOAC device states shouldn't be stored in GNVS, but be read from the
AOAC registers during runtime. Same for the EHCI controller's BAR0. The
location and size of the XHCI firmware can either be statically
determined at build-time or have coreboot generate ACPI objects that
contain the needed addresses. Since I can't easily test changes that
require booting to a desktop on Stoneyridge at the moment, only add
TODOs for now.

Signed-off-by: Felix Held 
Suggested-by: Kyösti Mälkki 
Change-Id: I3691b05606b9430cb60923780a6131993a9887d4
---
M src/soc/amd/stoneyridge/fch.c
1 file changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/60196/1

diff --git a/src/soc/amd/stoneyridge/fch.c b/src/soc/amd/stoneyridge/fch.c
index 16802ef..3037165 100644
--- a/src/soc/amd/stoneyridge/fch.c
+++ b/src/soc/amd/stoneyridge/fch.c
@@ -165,12 +165,14 @@
    gnvs->fw02 = fwaddr + XHCI_FW_BOOTRAM_SIZE;
    gnvs->fw03 = fwsize << 16;

+	/* TODO: This might break if the OS decides to re-allocate the PCI BARs. */
    gnvs->eh10 = pci_read_config32(SOC_EHCI1_DEV, PCI_BASE_ADDRESS_0)
    		& ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
 }

void fch_final(void *chip_info)
 {
+	/* TODO: The AOAC states and EHCI/XHCI addresses should be moved out of GNVS */
    struct global_nvs *gnvs = acpi_get_gnvs();
    if (gnvs) {
    	set_sb_aoac(&gnvs->aoac);