Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/19960 )
Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/#/c/19960/1/src/northbridge/intel/sandybridge/ra... File src/northbridge/intel/sandybridge/raminit_mrc.c:
PS1, Line 308: 0x5e04
MC_BIOS_DATA in northbridge/intel/sandybridge/raminit_common.h?
these 3 MCHBAR values (5000,5004,5008) are used for getting DRAM info for SNB thru SKL and repeated each time. I agree defining them once would be ideal but not sure where
PS1, Line 310: addr_decode_ch
This looks like channels, but we can have two dimms per channel, so should
added DIMM-B
PS1, Line 325: 122
Hrm - looks like we need an spd_ddr3.h file.
agreed, where to put it?
PS1, Line 328: same for all modules so use first
what if not all modules are populated?
addressed in patch 2
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Matt DeVillier (Code Review)