Change in coreboot[master]: mb/ti/beaglebone: Load romstage/ramstage from SD - coreboot-gerrit

11 Aug 2020

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44385 )
Change subject: mb/ti/beaglebone: Load romstage/ramstage from SD
......................................................................
mb/ti/beaglebone: Load romstage/ramstage from SD
Adds a "sd_media" boot_device to allow booting from the SD card. This
assumes that the generated "MLO" file is placed at a 128KB offset from
the start of the SD card, to allow for the MBR etc. to be at the start
of the SD card. Placing the MLO file here allows the AM335x boot ROM to
load and execute the bootblock stage as well, as 128KB is one of the
offsets the boot ROM checks when looking for the next stage to execute.
As part of this, a FMD for the Beaglebone has also been defined. It's
sized at 32M somewhat arbitrarily, as SD cards could allow for much
bigger payloads.
TEST: Beaglebone boots from bootblock into romstage. Romstage to
ramstage still doesn't work as it needs RAM initialization first.
Change-Id: I5f6901217fb974808e84aeb679af2f47eeae30fd
Signed-off-by: Sam Lewis sam.vr.lewis@gmail.com
---
M src/mainboard/ti/beaglebone-black/Kconfig
M src/mainboard/ti/beaglebone-black/Makefile.inc
A src/mainboard/ti/beaglebone-black/board.fmd
A src/mainboard/ti/beaglebone-black/sd_media.c
M src/soc/ti/am335x/Makefile.inc
D src/soc/ti/am335x/bootblock_media.c
M src/soc/ti/am335x/header.c
M src/soc/ti/am335x/header.h
M src/soc/ti/am335x/memlayout.ld
D src/soc/ti/am335x/nand.c
10 files changed, 172 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/44385/1

diff --git a/src/mainboard/ti/beaglebone-black/Kconfig b/src/mainboard/ti/beaglebone-black/Kconfig
index 5ff844e..a695942 100644
--- a/src/mainboard/ti/beaglebone-black/Kconfig
+++ b/src/mainboard/ti/beaglebone-black/Kconfig
@@ -5,8 +5,10 @@
 config BOARD_SPECIFIC_OPTIONS
    def_bool y
    select SOC_TI_AM335X
-	select BOARD_ROMSIZE_KB_4096
+	select BOARD_ROMSIZE_KB_32768
    select MISSING_BOARD_RESET
+	select COMMONLIB_STORAGE
+	select COMMONLIB_STORAGE_SD
config MAINBOARD_DIR
    string
@@ -28,4 +30,8 @@
    int
    default 0
+config FMDFILE
+	string
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd"
+
 endif # BOARD_TI_BEAGLEBONE_BLACK
diff --git a/src/mainboard/ti/beaglebone-black/Makefile.inc b/src/mainboard/ti/beaglebone-black/Makefile.inc
index a703939..0207a13 100644
--- a/src/mainboard/ti/beaglebone-black/Makefile.inc
+++ b/src/mainboard/ti/beaglebone-black/Makefile.inc
@@ -2,6 +2,9 @@
bootblock-y += bootblock.c
 bootblock-y += leds.c
-romstage-y += romstage.c
+bootblock-y += sd_media.c
-#ramstage-y += ramstage.c
+romstage-y += romstage.c
+romstage-y += sd_media.c
+
+ramstage-y += sd_media.c
diff --git a/src/mainboard/ti/beaglebone-black/board.fmd b/src/mainboard/ti/beaglebone-black/board.fmd
new file mode 100644
index 0000000..c0e4281
--- /dev/null
+++ b/src/mainboard/ti/beaglebone-black/board.fmd
@@ -0,0 +1,10 @@
+SDCARD@0x000 32M {
+    BIOS@0x0 109K {
+        BOOTBLOCK@0x0 20K
+    }
+
+    PAYLOAD {
+        FMAP 2K
+        COREBOOT(CBFS) 31M
+    }
+}
diff --git a/src/mainboard/ti/beaglebone-black/sd_media.c b/src/mainboard/ti/beaglebone-black/sd_media.c
new file mode 100644
index 0000000..7e04f21
--- /dev/null
+++ b/src/mainboard/ti/beaglebone-black/sd_media.c
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boot_device.h>
+#include <symbols.h>
+#include <console/console.h>
+#include <assert.h>
+#include <commonlib/storage/sd_mmc.h>
+#include <cbmem.h>
+
+#include <soc/ti/am335x/mmc.h>
+#include <soc/ti/am335x/header.h>
+
+// Where the coreboot image is expected to be located on the SD card
+// Only certain locations are allowed - check the AM335x technical reference
+// manual for more details.
+#define COREBOOT_IMAGE_OFFSET (128 * KiB)
+
+#define SD_BLOCK_SIZE 512
+
+static struct am335x_mmc_host sd_host;
+static struct storage_media media;
+
+static size_t partial_block_read(uint8_t *dest, uint64_t block, uint32_t offset, uint32_t count)
+{
+	static uint8_t overflow_block[SD_BLOCK_SIZE];
+
+	uint64_t blocks_read = storage_block_read(&media, block, 1, &overflow_block);
+
+	if (blocks_read != 1) {
+		printk(BIOS_ERR, "Expected to read 1 block but read: %llu\n", blocks_read);
+		return 0;
+	}
+
+	assert((offset + count) <= SD_BLOCK_SIZE);
+
+	int dest_index = 0;
+	for (int overflow_index = offset; overflow_index < (offset + count); overflow_index++)
+		dest[dest_index++] = overflow_block[overflow_index];
+
+	return count;
+}
+
+// This supports reads from a SD card that aren't necessarily aligned to the
+// sd block size
+static ssize_t sd_readat(const struct region_device *rdev, void *dest, size_t offset,
+			 size_t count)
+{
+	uint8_t *buffer = (uint8_t *)dest;
+
+	uint64_t block_start = offset / SD_BLOCK_SIZE;
+	uint64_t block_end = (offset + count) / SD_BLOCK_SIZE;
+	uint64_t blocks = block_end - block_start + 1;
+
+	// Read the last first, which might not be aligned on a SD block
+	uint32_t first_block_offset = offset % SD_BLOCK_SIZE;
+	size_t first_block_to_read = MIN(SD_BLOCK_SIZE - first_block_offset, count);
+	size_t bytes_read = partial_block_read(buffer, block_start, first_block_offset,
+					       first_block_to_read);
+
+	if (blocks == 1)
+		return bytes_read;
+
+	buffer += bytes_read;
+
+	if (blocks > 2) {
+		// Read all the "whole" blocks between the start and end blocks
+		uint64_t to_read = blocks - 2;
+		uint64_t blocks_read =
+			storage_block_read(&media, block_start + 1, to_read, (void *)buffer);
+
+		if (blocks_read != to_read) {
+			printk(BIOS_ERR, "Expecting to read %llu blocks but only read %llu\n",
+			       to_read, blocks_read);
+			return blocks_read * SD_BLOCK_SIZE;
+		}
+
+		buffer += to_read * SD_BLOCK_SIZE;
+		bytes_read += to_read * SD_BLOCK_SIZE;
+	}
+
+	// Read the last block, which might not be aligned on a SD block
+	bytes_read += partial_block_read(buffer, block_end, 0, count - bytes_read);
+
+	return bytes_read;
+}
+
+static const struct region_device_ops am335x_sd_ops = {
+	.mmap = mmap_helper_rdev_mmap,
+	.munmap = mmap_helper_rdev_munmap,
+	.readat = sd_readat,
+};
+
+extern struct omap_image_headers headers;
+
+static struct mmap_helper_region_device sd_mdev = MMAP_HELPER_REGION_INIT(
+	&am335x_sd_ops, COREBOOT_IMAGE_OFFSET + sizeof(headers), CONFIG_ROM_SIZE);
+
+static bool init_done = false;
+
+void boot_device_init(void)
+{
+	if (init_done)
+		return;
+
+	sd_host.sd_clock_hz = 96000000;
+	sd_host.reg = (void *)MMCHS0_BASE;
+	am335x_mmc_init_storage(&sd_host);
+	storage_setup_media(&media, &sd_host.sd_mmc_ctrlr);
+	storage_display_setup(&media);
+
+	if (ENV_BOOTBLOCK) {
+		mmap_helper_device_init(&sd_mdev, _cbfs_cache, REGION_SIZE(cbfs_cache));
+	} else {
+		mmap_helper_device_init(&sd_mdev, _postram_cbfs_cache,
+					REGION_SIZE(postram_cbfs_cache));
+	}
+
+	init_done = true;
+}
+
+const struct region_device *boot_device_ro(void)
+{
+	return &sd_mdev.rdev;
+}
diff --git a/src/soc/ti/am335x/Makefile.inc b/src/soc/ti/am335x/Makefile.inc
index f5ebb7a..990a61e 100644
--- a/src/soc/ti/am335x/Makefile.inc
+++ b/src/soc/ti/am335x/Makefile.inc
@@ -1,16 +1,16 @@
 bootblock-y	+= bootblock.c
-bootblock-y	+= bootblock_media.c
 bootblock-y	+= timer.c
 bootblock-y	+= gpio.c
 bootblock-y	+= pinmux.c
+bootblock-y += mmc.c
-romstage-y	+= nand.c
 romstage-y	+= cbmem.c
 romstage-y	+= timer.c
+romstage-y	+= mmc.c
ramstage-y	+= timer.c
-ramstage-y	+= nand.c
-ramstage-y  += soc.c
+ramstage-y	+= soc.c
+ramstage-y 	+= mmc.c
bootblock-y	+= uart.c
 romstage-y	+= uart.c
diff --git a/src/soc/ti/am335x/bootblock_media.c b/src/soc/ti/am335x/bootblock_media.c
deleted file mode 100644
index b7e49a6..0000000
--- a/src/soc/ti/am335x/bootblock_media.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <boot_device.h>
-#include <symbols.h>
-
-static const struct mem_region_device boot_dev =
-	MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE);
-
-const struct region_device *boot_device_ro(void)
-{
-	return &boot_dev.rdev;
-}
diff --git a/src/soc/ti/am335x/header.c b/src/soc/ti/am335x/header.c
index c0a7589..f49598b 100644
--- a/src/soc/ti/am335x/header.c
+++ b/src/soc/ti/am335x/header.c
@@ -5,23 +5,6 @@
#include "header.h"
-struct config_headers {
-	// The table of contents.
-	struct configuration_header_toc_item toc_chsettings;
-	struct configuration_header_toc_item toc_end;
-
-	// An inert instance of chsettings.
-	struct configuration_header_settings chsettings;
-} __packed;
-
-struct omap_image_headers {
-	union {
-		struct config_headers config_headers;
-		uint8_t bytes[512];
-	};
-	struct gp_device_header image_header;
-};
-
 // A symbol which defines how much of the image the iROM should load.
 extern char header_load_size;
diff --git a/src/soc/ti/am335x/header.h b/src/soc/ti/am335x/header.h
index a0a54ad..84e09f3 100644
--- a/src/soc/ti/am335x/header.h
+++ b/src/soc/ti/am335x/header.h
@@ -47,4 +47,21 @@
    uint32_t destination;
 } __packed;
+struct config_headers {
+	// The table of contents.
+	struct configuration_header_toc_item toc_chsettings;
+	struct configuration_header_toc_item toc_end;
+
+	// An inert instance of chsettings.
+	struct configuration_header_settings chsettings;
+} __packed;
+
+struct omap_image_headers {
+	union {
+		struct config_headers config_headers;
+		uint8_t bytes[512];
+	};
+	struct gp_device_header image_header;
+};
+
 #endif
diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld
index 16770a5..40c0836 100644
--- a/src/soc/ti/am335x/memlayout.ld
+++ b/src/soc/ti/am335x/memlayout.ld
@@ -12,11 +12,14 @@
    TTB(0x402F8000, 16K)
    ROMSTAGE(0x402F8000+16K, 40K)
+	PRERAM_CBFS_CACHE(0x402F8000+16K+40K, 20K)
+
    STACK(0x4030be00, 4K)
    SRAM_END(0x40310000)
-	DRAM_START(0x80000000)
-	RAMSTAGE(0x80200000, 192K)
+	DRAM_START(0x80000000)
+	RAMSTAGE(0x80000000, 2M)
+	POSTRAM_CBFS_CACHE(0x80200000, 32M)
#ifdef OMAP_HEADER
    .header : {
diff --git a/src/soc/ti/am335x/nand.c b/src/soc/ti/am335x/nand.c
deleted file mode 100644
index a7029a0..0000000
--- a/src/soc/ti/am335x/nand.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <boot_device.h>
-
-const struct region_device *boot_device_ro(void)
-{
-	/* FIXME: add support for reading coreboot from NAND */
-	return NULL;
-}
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5f6901217fb974808e84aeb679af2f47eeae30fd
Gerrit-Change-Number: 44385
Gerrit-PatchSet: 1
Gerrit-Owner: Sam Lewis sam.vr.lewis@gmail.com
Gerrit-Reviewer: Julius Werner jwerner@chromium.org
Gerrit-Reviewer: Martin Roth martinroth@google.com
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-MessageType: newchange



    